• «u t
-1021042
PROJECT
r\
APOLLO
LUNAR EXCURSION MODULE
PRIMARY GUIDANCE, NAVIGATION
AND CONTROL SYSTEM MANUA
VOLUME I
ELECTR0NICS
DIVISION OF GENERAL MOTORS
'J.
INITIAL TDRR 26432
TYPE I
APPROVED BY NASA
APOLLO .
LUNAR EXCURSION MODULE
4
PRIMARY
GUIDANCE, NAVIGATION,
AND CONTROL SYSTEM «
MANUAL
VOLUME I OF II
PREPARED FOR
NATIONAL AERONAUTICS AND SPACE ADMINISTRATION *
MANNED SPACECRAFT CENTER
BY
AC ELECTRONICS
DIVISION OF GENERAL MOTORS
Ml LWAUKEE,WISCONSI N 53201
*
t
' y °
NASA CONTRACT NAS 9-497
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Record of Revisions
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Date
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Number
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Approval
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
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ND-1021042
MANUAL
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
CONTENTS
Chapter Page
Volume I
1 SYSTEM TIE-IN . 1-1
1-1 Scope . 1_1
1-2 LEM Mission . 1-1
1-2.1 Separation and Transfer Orbit Insertion . 1-1
1-2.2 Descent Coast . 1-1
1-2.3 Powered Descent and Landing . 1-2
1-2.4 Lunar Stay . 1-3
1-2.5 Launch and Powered Ascent . 1-3
1-2.6 Rendezvous and Docking . 1-3
1-3 LEM Structure . 1-4
1-3.1 Ascent Stage . 1-4
1-3.2 Descent Stage . 1-7
1-4 LEM Systems . 1-7
1-4.1 Primary Guidance, Navigation, and Control System. . 1-7
1-4.2 Stabilization and Control System . 1-8
1-4.3 Propulsion System . 1-9
1-4.4 Reaction Control System . 1-9
1-4.5 Electrical Power System . 1-10
1-4.6 Environmental Control System . 1-10
1-4.7 Communications and Instrumentation System . 1-10
1- 5 PGNCS Interface . 1-10
1-5.1 Systems . 1-12
1-5.2 Displays and Controls . 1-12
1- 5.3 Landing Radar . 1-12
2 SYSTEM AND SUBSYSTEM FUNCTIONAL ANALYSIS . 2-1
2- 1 Scope . 2-1
2-2 Primary Guidance, Navigation, and Control System . 2-1
2-3 LEM and PGNCS Axes . 2-2
2- 3.1 LEM Spacecraft Axes . 2-2
2-3.2 Navigation Base Axes . 2-2
2-3.3 Inertial Axes . 2-2
I-xi
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ND-1021042
MANUAL
CONTENTS (cont)
Chapter Page
2-4 Inertial Subsystem . 2-4
2-4.1 Stabilization Loop . 2-5
2-4.2 Fine Align Electronics . 2-9
2-4.3 Accelerometer Loop . 2-14
2-4.4 IMU Temperature Control System . 2-21
2-4.5 ISS Modes of Operation . 2-25
2-4.6 ISS Power Supplies . 2-37
2-5 LEM Optical Rendezvous Subsystem . 2-41
2- 6 Computer Subsystem . 2-42
2-6.1 Programs . 2-47
2-6.2 Machine Instructions . 2-48
2-6.3 Timer . 2-50
2-6.4 Sequence Generator . 2-51
2-6.5 Central Processor . 2-52
2-6.6 Priority Control . 2-54
2-6.7 Input-Output . 2-55
2-6.8 Memory . 2-56
2-6.9 Power Supplies . 2-58
2- 6.10 Display and Keyboard . 2-59
3 PHYSICAL DESCRIPTION . 3-1
3- 1 Scope . 3-1
3-2 PGNCS Interconnect Harness . 3-1
3-3 Navigation Base Assembly . 3-5
3-4 Inertial Measuring Unit . 3-5
3- 4.1 Stable Member . 3-6
3-4.2 Middle Gimbal . 3-7
3-4.3 Outer Gimbal . 3-7
3-4.4 Supporting Gimbal . 3-7
3-4.5 Inter-Gimbal Assemblies . 3-10
3-5 Optical Tracker . 3-10
3-6 Luminous Beacon . 3-12
3-7 Pulse Torque Assembly . 3-13
3-8 Power and Servo Assembly . 3-17
I-xii
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
CONTENTS (cont)
Chapter Page
3-9 LEM Guidance Computer . 3-20
3-9.1 Logic Tray A . 3-21
3- 9.2 Tray B . 3-21
3-10 Coupling Data Unit . 3-22
3-11 Signal Conditioner . 3-24
3- 12 Display and Keyboard . 3-24
4 COMPONENT THEORY OF OPERATION . 4-1
4- 1 Scope . 4-1
4-2 Apollo II Inertial Reference Integrating Gyro . 4-1
4- 2. 1 Gyro Wheel Assembly . 4-3
4-2.2 Float Assembly . 4-3
4-2.3 Case . 4-4
4-2.4 Normalizing Network . 4-4
4-2.5 Apollo II IRIG Ducosyns . 4-4
4-3 16 Pulsed Integrating Pendulum . 4-10
4-3. 1 Float Assembly . 4-13
4-3.2 Housing Assembly . 4-13
4-3.3 Outer Case Assembly . 4-13
4-3.4 Normalizing Network . 4-13
4-3.5 PIP Ducosyns . 4-13
4-4 Coupling Data Unit . 4-15
4-4. 1 Coarse System Module . 4-15
4-4. 2 Quadrant Selector Module . 4-23
4-4.3 Main Summing Amplifier and Quadrature
Rejection Module . 4-29
4-4.4 Read Counter Module . 4-32
4-4. 5 Error Angle Counter and Logic Module . 4-33
4-4. 6 Digital Mode Module . 4-34
4-4.7 Interrogate Module . 4-35
4-4.8 Digital to Analog Converter . 4-37
4-4. 9 Mode Module . 4-41
4-4. 10 4 VDC Power Supply . 4-43
4-5 LEM Guidance Computer . 4-44
4-5. 1 Programs . 4-44
I-xiii
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ND-1021042
MANUAL
CONTENTS (cont)
Chapter Page
4-5.2 Machine Instructions . 4-49
4-5.3 Timer . 4-204
4-5.4 Sequence Generator . 4-229
Volume II
4-5. 5 Central Processor . 4-365
4-5.6 Priority Control . 4-428
4-5.7 Input -Output . 4-435
4-5.8 Memory . 4-439
4-5.9 Power Supply . 4-460
4- 5. 10 Display and Keyboard . 4-491
4-6 Signal Conditioner . 4-492
4- 7 LEM Optical Rendezvous Subsystem . 4-492
5 MISSION OPERATIONS . 5-1
5- 1 Scope . 5-1
5-2 IMU Coarse Alignment . 5-1
5-3 IMU Fine Alignment . 5-1
5-4 Transfer Orbit . 5-2
5-5 Powered Descent . 5-2
5- 5.1 Phase I - Braking . 5-2
5-5.2 Phase II - Final Approach . 5-2
5-5.3 Phase III - Landing . 5-7
5-6 Lunar Stay . 5-7
5-7 Ascent . 5-7
5- 8 Rendezvous and Docking . 5-7
6 CHECKOUT AND MAINTENANCE EQUIPMENT . 6-1
6- 1 Scope . 6-1
7 CHECKOUT . 7-1
7- 1 Scope . 7-1
7-2 Primary Guidance, Navigation, and Control System . 7-1
7-2.1 Preparation . 7-1
7-2.2 Checkout . 7-1
7-2.3 Test Descriptions . 7-1
I-xiv
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
CONTENTS (cont)
Chapter Page
7-3 Inertial Subsystem . 7-1
7-3. 1 Preparation . 7-1
7-3.2 Checkout . 7-2
7-4 Computer Subsystem . 7-2
7-4. 1 Preparation . 7-2
7- 4.2 Checkout . 7-2
7- 5 LEM Optical Rendezvous Subsystem . 7-2
8 MAINTENANCE . 8-1
8- 1 Scope . 8-1
8-2 Maintenance Concept . 8-1
8-3 Malfunction Isolation . 8-2
8-4 Double Verification . 8-2
8- 4. 1 Malfunction Verification . 8-2
8-4. 2 Repair Verification . 8-6
8-5 Pre-Installation Acceptance Test . 8-6
8-6 Removal and Replacement . 8-6
8-7 Maintenance Schedule . 8-6
8-8 Optical Cleaning . . . 8-6
APPENDIX A LIST OF TECHNICAL TERMS AND ABBREVIATIONS . A-l
APPENDIX B RELATED DOCUMENTATION . B-l/B-2
APPENDIX C LOGIC SYMBOLS . C-l
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ND-1021042
MANUAL
ILLUSTRATIONS
Volume I
Figure Page
1-1 LEM Primary Guidance, Navigation, and Control System . .I-xxxiii/I-xxxiv
1-2 LEM Mission Phases . 1-2
1-3 LEM . 1-5
1-4 LEM External Dimensions . 1-6
1- 5 LEM PGNCS Functional Interface, Block Diagram . 1-11
2- 1 PGNCS Subsystems Interface, Block Diagram . 2-3
2-2 LEM and PGNCS Axes . 2-4
2-3 ISS, Block Diagram . 2-6
2-4 Stabilization Loop, Block Diagram . 2-7
2-5 Fine Align Electronics -Computer Inputs . 2-9
2-6 Fine Align Electronics -Gyro Selection . 2-10
2-7 Binary Current Switch . 2-12
2-8 DC Differential Amplifier and Precision Voltage Reference . 2-13
2-9 Accelerometer Loop . 2-14
2-10 AC Differential Amplifier and Interrogator Module . 2-16
2-11 Accelerometer Timing . 2-19
2-12 PIPA Calibration Module . 2-20
2-13 IMU Temperature Control System . 2-23/2-24
2-14 ISS-CDU Moding . 2-27/2-28
2-15 IMU Cage Mode . 2-31/2-32
2-16 Display Inertial Data Mode . 2-36
2-17 Pulse Torque Power Supply . 2-38
2-18 -28 VDC Power Supply . 2-40
2-19 800 CPS Power Supply . 2-40
2-20 3, 200 CPS Power Supply . 2-42
2-21 Computer Subsystem, Block Diagram . 2-43/2-44
2-22 Program Organization . 2-47
2-23 Timer, Block Diagram . 2-51
2-24 Sequence Generator, Block Diagram . 2-52
2-25 Central Processor, Block Diagram . 2-53
2-26 Priority Control, Block Diagram . 2-54
2-27 Input -Output, Block Diagram . 2-55
2-28 Memory, Block Diagram . 2-57
2-29 Power Supplies, Block Diagram . 2-58
2-30 Display and Keyboard (DSKY), Block Diagram . 2-59
I-xvii
ND-1021042
ILLUSTRATIONS (cont)
Figure Page
3-1 Location of LEM PGNCS Components . 3-3
3-2 Navigation Base Assembly . 3-5
3-3 Inertial Measuring Unit . 3-6
3-4 IMU Stable Member . 3-8
3-5 Optical Tracker . 3-11
3-6 Luminous Beacon . 3-12
3-7 Pulse Torque Assembly . 3-13
3-8 Power and Servo Assembly . 3-17
3-9 LEM Guidance Computer . 3-20
3-10 Logic Tray A . 3-21
3-11 Tray B . 3-22
3-12 Coupling Data Unit . 3-23
3-13 CDU Module Locations . 3-25
3- 14 Display and Keyboard . 3-27
4- 1 Apollo II IRIG, Simplified Cutaway View . 4-2
4-2 Apollo II IRIG Normalizing Network . 4-5
4-3 IRIG Signal Generator and Suspension Microsyn . 4-7
4-4 IRIG Torque Generator and Suspension Microsyn . 4-8
4-5 Ducosyn RLC Equivalent Circuit . 4-9
4-6 Definition of 16 PIP Axes . 4-11
4-7 Result of Acceleration Along Input Axis . 4-12
4-8 PIP Torque Generator . 4-14
4-9 Read Counter Relationship to Coarse and Fine System Switching. 4-16
4-10 Coarse System Module, Block Diagram . 4-17
4-11 Resolver Sine and Cosine Phase Relationships . 4-18
4-12 Coarse Switch Circuit and Logic Equations . 4-19
4-13 Coarse Switching Diagram . 4-20
4-14 Quadrant Selector Module, Block Diagram . 4-25
4-15 Fine Switching Diagram . 4-26
4-16 Main Summing Amplifier and Quadrature Rejection Module,
Block Diagram . 4-30
4-17 Simplified 3 Bit Converter and Switch Configurations . 4-39
4-18 4 VDC Power Supply, Block Diagram . 4-44
4-19 Basic Instruction Word Format . 4-50
4-20 Subinstruction TC0, Data Transfer Diagram . 4-107
4-21 Subinstruction TC0, with Implied Address Code EXTEND,
Data Transfer Diagram . 4-108
4-22 Subinstruction CCS0, Branch on Quantity Greater Than
Plus Zero, Data Transfer Diagram . 4-109
4-23 Subinstruction CCS0, Branch on Minus Zero, Data
Transfer Diagram . 4-110
4-24 Subinstruction CCS0, Branch on Quantity Less Than
Minus Zero, Data Transfer Diagram . 4-111
4-25 Subinstruction CCS0, Branch on Plus 0, Data Transfer Diagram 4-112
4-26 Subinstruction STD2, Data Transfer Diagram . 4-113
4-27 Subinstruction STD2, with Implied Address Code INHINT,
Data Transfer Diagram . 4-114
I-xviii
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ND-1021042
MANUAL
ILLUSTRATIONS (cont)
Figure Page
4-28 Subinstruction STD2, with Implied Address Code RE LINT,
Data Transfer Diagram . 4-115
4-29 Subinstruction STD2, with Implied Address Code EXTEND,
Data Transfer Diagram . 4-116
4-30 Subinstruction TCFO, Data Transfer Diagram . 4-117
4-31 Subinstruction TCFO, with Implied Address Code EXTEND,
Data Transfer Diagram . 4-118
4-32 Subinstruction DASO, without Overflow or Underflow, Data
Transfer Diagram . 4-119
4-33 Subinstruction DAS1, without Overflow or Underflow, Data
Transfer Diagram . 4-120
4-34 Subinstruction DASO, with Overflow and Implied Address
Code DDOUBL, Data Transfer Diagram . 4-121
4-35 Subinstruction DAS1, with Overflow and Implied Address
Code DDOUBL, Data Transfer Diagram . 4-122
4-36 Subinstruction DASO, with Underflow, Data Transfer Diagram. . 4-123
4-37 Subinstruction DAS1, with Underflow, Data Transfer Diagram. . 4-124
4-38 Subinstruction LXCHO, Data Transfer Diagram . 4-125
4-39 Subinstruction INCRO, Data Transfer Diagram . 4-126
4-40 Subinstruction ADSO, Data Transfer Diagram . 4-127
4-41 Subinstruction CAO, Data Transfer Diagram . 4-128
4-42 Subinstruction CSO, Data Transfer Diagram . 4-129
4-43 Subinstruction NDXO, Data Transfer Diagram . 4-130
4-44 Subinstruction NDX1, Data Transfer Diagram . 4-131
4-45 Subinstruction NDXO with Implied Address Code RESUME,
Data Transfer Diagram . 4-132
4-46 Subinstruction RSM3, Data Transfer Diagram . 4-133
4-47 Subinstruction RSM3 with Implied Address Code EXTEND,
Data Transfer Diagram . 4-134
4-48 Subinstruction DXCHO, Data Transfer Diagram . 4-135
4-49 Subinstruction DXCH1, Data Transfer Diagram . 4-136
4-50 Subinstruction TS0 without Overflow or Underflow, Data
Transfer Diagram . 4-137
4-51 Subinstruction TS0 with Overflow, Data Transfer Diagram . . . 4-138
4-52 Subinstruction TS0 with Underflow, Data Transfer Diagram . . . 4-139
4-53 Subinstruction XCH0, Data Transfer Diagram . 4-140
4-54 Subinstruction ADO, Data Transfer Diagram . 4-141
4-55 Subinstruction MSK0, Data Transfer Diagram . 4-142
4-56 Subinstruction RE ADO, Data Transfer Diagram . 4-143
4-57 Subinstruction WRITE 0, Data Transfer Diagram . 4-144
4-58 Subinstruction RAND0, Data Transfer Diagram . 4-145
4-59 Subinstruction WAND0, Data Transfer Diagram . 4-146
4-60 Subinstruction RORO, Data Transfer Diagram . 4-147
4-61 Subinstruction WORO, Data Transfer Diagram . 4-148
4-62 Subinstruction RXORO, Data Transfer Diagram . 4-149
4-63 Subinstruction RUPT0, Data Transfer Diagram . 4-150
I-xix
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ND-1021042
MANUAL
ILLUSTRATIONS (cont)
Figure Page
4-64 Subinstruction RUPT1, Data Transfer Diagram . 4-151
4-65 Subinstruction DVO, Data Transfer Diagram . 4-152
4-66 Subinstruction DV1, Data Transfer Diagram . 4-153
4-67 Subinstruction DV3, Data Transfer Diagram . 4-154
4-68 Subinstruction DV7, Data Transfer Diagram . 4-155
4-69 Subinstruction DV6, Data Transfer Diagram . 4-156
4-70 Subinstruction DV4, Data Transfer Diagram . 4-157
4-71 Subinstruction BZFO with Branch on Non-Zero Quantity,
Data Transfer Diagram . 4-158
4-72 Subinstruction BZFO with Branch on Plus Zero, Data
Transfer Diagram . 4-159
4-73 Subinstruction BZFO with Implied Address Code EXTEND,
Data Transfer Diagram . 4-160
4-74 Subinstruction MSUO with Positive Resultant, Data
Transfer Diagram . 4-161
4-75 Subinstruction MSUO with Negative Resultant, Data
Transfer Diagram . 4-162
4-76 Subinstruction QXCHO, Data Transfer Diagram . 4-163
4-77 Subinstruction AUGO with Positive Quantity, Data
Transfer Diagram . 4-164
4-78 Subinstruction AUGO with Negative Quantity, Data
Transfer Diagram . 4-165
4-79 Subinstruction DIMO with Positive Quantity, Data
Transfer Diagram . 4-166
4-80 Subinstruction DIMO with Negative Quantity, Data
Transfer Diagram . 4-167
4-81 Subinstruction DCAO, Data Transfer Diagram . 4-168
4-82 Subinstruction DCA1, Data Transfer Diagram . 4-169
4-83 Subinstruction DSCO, Data Transfer Diagram . 4-170
4-84 Subinstruction DCS1, Data Transfer Diagram . 4-171
4-85 Subinstruction NDXXO, Data Transfer Diagram . 4-172
4-86 Subinstruction NDXX1, Data Transfer Diagram . 4-173
4-87 Subinstruction SUO, Data Transfer Diagram . 4-174
4-88 Subinstruction BZMFO with Quantity Greater Than
Plus Zero, Data Transfer Diagram . 4-175
4-89 Subinstruction BZMFO with Plus Zero, Data Transfer Diagram . 4-176
4-90 Subinstruction BZMFO with Negative Quantity, Data
Transfer Diagram . 4-177
4-91 Subinstruction BZMFO with Implied Address Code EXTEND,
Data Transfer Diagram . 4-178
4-92 Subinstruction MP0 with Two Positive Numbers, Data
Transfer Diagram . 4-179
I-xx
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
ILLUSTRATIONS (cont)
Figure Page
4-93 Subinstruction MPO with Positive Number in A and
Negative Number in E, Data Transfer Diagram . 4-180
4-94 Subinstruction MPO with Negative Number in A and
Positive Number in E, Data Transfer Diagram . 4-181
4-95 Subinstruction MPO with Two Negative Numbers, Data
Transfer Diagram . 4-182
4-96 Subinstruction MP1, Data Transfer Diagram . 4-183
4-97 Subinstruction MP3, Data Transfer Diagram . 4-184
4-98 Subinstruction MP3 with Implied Address Code EXTEND,
Data Transfer Diagram . 4-185
4-99 Subinstruction GOJ1, Data Transfer Diagram . 4-186
4-100 Subinstruction PINC, Data Transfer Diagram . 4-187
4-101 Subinstruction MINC, Data Transfer Diagram . 4-188
4-102 Subinstruction DINC with Positive Quantity, Data
Transfer Diagram . 4-189
4-103 Subinstruction DINC with Plus Zero, Data Transfer Diagram . . 4-190
4-104 Subinstruction DINC with Negative Quantity, Data
Transfer Diagram . 4-191
4-105 Subinstruction DINC with Minus Zero, Data Transfer Diagram . 4-192
4-106 Subinstruction PCDU, Data Transfer Diagram . 4-193
4-107 Subinstruction MCDU, Data Transfer Diagram . 4-194
4-108 Subinstruction SHINC, Data Transfer Diagram . 4-195
4-109 Subinstruction SHANC, Data Transfer Diagram . 4-196
4-110 Subinstruction TCSAJ3, Data Transfer Diagram . 4-197
4-111 Subinstruction FETCH0, Data Transfer Diagram . 4-198
4-112 Subinstruction FETCH1, Data Transfer Diagram . 4-199
4-113 Subinstruction STOREO, Data Transfer Diagram . 4-200
4-114 Subinstruction STORE 1, Data Transfer Diagram . 4-201
4-115 Subinstruction INOTRD, Data Transfer Diagram . 4-202
4-116 Subinstruction INOTLD, Data Transfer Diagram . 4-203
4-117 Timer, Functional Diagram . 4-205/4-206
4-118 LGC Oscillator, Schematic Diagram . 4-209/4-210
4-119 Clock Divider Logic . 4-213/4-214
4-120 Scaler . 4-219/4-220
4-121 Scaler Waveforms . 4-223
4-122 Time Pulse Generator Logic . 4-227/4-228
4-123 Time Pulse Generator Waveforms . 4-230
4-124 Sync and Timing Logic . 4-231/4-232
Volume II
4-125 Order Code Processor, Block Diagram . 4-233
4-126 Command Generator, Block Diagram . 4-235
4-127 Control Pulse Generator, Block Diagram . 4-236
I-xxi
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ILLUSTRATIONS (cont)
Figure Page
4-128 Register SQ Control, Logic Diagram . 4-239/4-240
4-129 Register SW and Decoder, Logic Diagram . 4-243/4-244
4-130 Stage Counter and Decoder, Logic Diagram . 4-247/4-248
4-131 Subinstruction Decoder, Logic Diagram . 4-257/4-258
4-132 Instruction Decoder, Logic Diagram . 4-269/4-270
4-133 Counter and Peripheral Instruction Control Logic . 4-273/4-274
4-134 Crosspoint Generator, Logic Diagram . 4-281/4-282
4-135 Control Pulse Gates, Logic Diagram . 4-351
4-136 Branch Control, Logic Diagram . 4-359/4-360
4-137 Word Formats . 4-366
4-138 Central Processor, Functional Diagram . 4-369/4-370
4-139 Flip-Flop Register, Single Bit Positions . 4-371
4-140 Write, Clear, and Read Timing . 4-372
4-141 Addressable Registers Service . 4-373/4-374
4-142 Flip-Flop Registers . 4-375/4-376
4-143 Register A Service . 4-391/4-392
4-144 Register L Service . 4-395
4-145 Register Q Service . 4-396
4-146 Register Z Service . 4-397
4-147 Z15 and Z16 Set (Sign Test During DV1) . 4-398
4-148 Register B Service . 4-399
4-149 Register G Service . 4-401/4-402
4-150 Editing Control . 4-403
4-151 Editing Transformations . 4-404
4-152 Adder Service (Registers X and Y) . 4-409/4-410
4-153 Carry Logic . 4-412
4-154 Memory Address Register (S) . 4-417/4-418
4-155 Address Decoder . 4-421/4-422
4-156 Counter Address Signals . 4-427
4-157 Parity Logic . 4-429/4-430
4-158 Priority Control, Functional Block Diagram . 4-433/4-434
4-159 Input-Output Channels, Functional Diagram . 4-437/4-438
4-160 Inlink Functional Diagram . 4-440
4-161 Outlink, Functional Diagram . 4-441/4-442
4-162 Erasable Memory, Functional Diagram . 4-445/4-446
4-163 Erasable Memory Timing Diagram . 4-448
4-164 X and Y Selection, Simplified Diagram . 4-451/4-452
4-165 Fixed Memory, Functional Diagram . 4-453/4-454
4-166 Fixed Memory, Timing Diagram . 4-459
4-167 Power Supply, Functional Diagram . 4-461/4-462
I-xxii
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
ILLUSTRATIONS (cont)
Figure Page
4-168 +4 VDC Power Supply, Schematic Diagram . 4-465/4-466
4-169 +14 VDC Power Supply, Schematic Diagram . 4-469/4-470
4-170 Alarm Detection Circuits, Schematic Diagram . 4-487/4-488
4- 171 DSKY, Functional Diagram . 4-493/4-494
5- 1 LEM Mission . 5-3/5-4
5-2 LEM IMU Coarse Alignment . 5-3
5-3 LEM IMU Fine Alignment . 5-3
5-4 Powered Descent . 5-6
5- 5 Powered Ascent . 5-8
6- 1 Typical Universal Test Station Layout . 6-11/6-12
7- 1 Primary Guidance, Navigation, and Control System Master
Checkout Flowgram . 7-17/7-18
7-2 Primary Guidance, Navigation, and Control System
Checkout Preparation Flowgram . 7-19/7-20
7-3 Primary Guidance, Navigation, and Control System
Checkout Flowgram . 7-21/7-22
7-4 Inertial Subsystem Master Checkout Flowgram . 7-23/7-24
7-5 Inertial Subsystem Checkout Preparation Flowgram . 7-25/7-26
7- 6 Inertial Subsystem Checkout Flowgram . 7-27/7-28
8- 1 Maintenance Flowgram . 8-3
C-l NOR Gate Symbols . C-2
C-2 NOR Gate Schematic . C-4
C-3 NOR Gate Flip-Flop . C-5
C-4 Logic Diagram Symbols . C-6
I-xxiii/I-xxiv
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
TABLES
Number
Volume I
Page
1-1 SCS Interface Signals . 1-13
1— II Displays and Controls . 1-14
1 -ITT Description of Landing Radar Interface Signals . . 1-16
2-1
Instruction Classes
2-49
3-1 LEM PGNCS Components . 3-1
3-II PGNCS Harness Interconnections . 3-4
3-ID Locations and Functions of IMU Electronics . 3-9
3-IV Locations and Functions of PTA Modules . 3-14
3-V PTA Test Points . 3-16
3- VI Locations and Functions of PSA Modules . 3-18
3-VD Functions of CDU Modules . 3-26
3-VHI DSKY Controls and Indicators . 3-28
4-1 Program Storage Allocation . 4-45/4-46
4-H Functional Organization of Machine Instructions . 4-53
4-HI Counter Instructions . 4-59
4-IV Machine Instructions, Alphabetical Listing . 4-60
4-V Subinstructions . 4-68
4-VI Control Pulses . 4-73
4-VH Subinstruction Codes and Control Pulses . 4-81/4-82
4-VHI Scaler Outputs (Stages 1-17) . 4-225
Volume II
4-IX Commands Per Sub instruction . 4-251
4-X Subinstructions Per Command . 4-264
4-XI Counter Cell Signals . 4-278
4-XU Subinstruction CCSO . 4-280
4-XIH Subinstruction DVO . 4-303
4-XIV Subinstruction DV1, Part 1 . 4-304
4-XV Subinstructions DV3, DV7, and DV6, Part 1 4-305
4-XVI Subinstructions DV1, DV3, DV7, and DV6, Part 2 . 4-306
4-XVH Subinstruction DV4 . 4-307
4-XVIH Subinstruction MP0 . 4-309
4-XIX Subinstruction MP1 . 4-310
I-xxv
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
TABLES (cont)
Number Page
4-XX Subinstruction MP3 . 4-311
4-XXI Crosspoint Pulse ZIP . 4-312
4-XXH Subinstruction STD2 . 4-314
4-XXHI Subinstruction TCO . 4-314
4-XXIV Subinstruction TCFO . 4-315
4-XXV Subinstruction TCSAJ3 . 4-315
4-XXVI Subinstruction GOJ1 . 4-315
4-XXVII Subinstruction DASO . 4-316
4-XXVm Subinstruction DAS1 . 4-317
4-XXIX Subinstruction LXCHO . 4-318
4-XXX Subinstruction INCRO . 4-318
4-XXXI Subinstruction ADSO . 4-319
4-XXXn Subinstructions CAO and DCAl . 4-320
4-XXXHI Subinstructions CSO and DCS1 . 4-320
4-XXXTV Subinstruction NDXO . 4-321
4-XXXV Subinstruction RSM3 . 4-321
4-XXXVI Subinstruction NDX1 . 4-322
4-XXXVD Subinstruction XCHO . 4-323
4-XXX VIII Subinstruction DXCHO . 4-324
4-XXXIX Subinstruction DXCH1 . 4-324
4-XL Subinstruction TSO . 4-325
4-XLI Subinstruction ADO . 4-326
4-XLII Subinstruction MASKO . 4-327
4-XLIH Subinstruction BZFO . 4-328
4-XLIV Subinstruction MSUO . 4-329
4-XLV Subinstruction QXCHO . 4-330
4-XLVI Subinstruction AUGO . 4-330
4-XLVII Subinstruction DIMO . 4-331
4-XLVHI Subinstruction DCAO . 4-332
4-XLIX Subinstruction DC SO . 4-333
4-L Subinstruction SUO . 4-334
4-LI Subinstruction NDXXO . 4-334
4-LII Subinstruction NDXX1 . 4-335
4- LIH Subinstruction BZMFO . 4-336
4-LIV Subinstruction READO . 4-337
4-LV Subinstruction WRITE 0 . 4-338
4-LVI Subinstruction RANDO . 4-339
4-LVII Subinstruction WANDO . 4-340
4-LVHI Subinstruction RORO . 4-341
4-UX Subinstruction WORO . 4-341
I-xxvi
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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TABLES (cont)
Number Page
4- LX Subinstruction RXORO . 4-342
4-LXI Subinstruction RUPTO . 4-343
4-LXII Subinstruction RUPT1 . 4-343
4-LXIII Subinstruction PINC . 4-344
4-LXTV Subinstruction MINC . 4-344
4-LXV Subinstruction PC DU . 4-345
4-LXVI Subinstruction MCDU . 4-345
4-LXVH Subinstruction DINC . 4-346
4-LXVEI Subinstruction SHINC . 4-347
4-LXIX Subinstruction SHANC . 4-347
4-LXX Subinstruction INOTRD . 4-348
4-LXXI Subinstruction INOTLD . 4-348
4-LXXH Subinstructions FETCHO and STOREO . 4-349
4-LXXHI Subinstruction FETCH1 . 4-349
4-LXXIV Subinstruction STORE 1 . 4-350
4-LXXV Control Pulse Orgin . 4-357
4-LXXVI Register A and L Write Line Inputs . 4-393
4-LXXVH Write Amplifiers External Inputs . 4-413/4-414
4-LXXVIII Erasable Memory Address Selection . 4-425/4-426
4-LXXIX E Addressing . 4-447
4-LXXX F Addressing . 4-455
4-LXXXI Power Distribution . 4-472
6-1 Checkout and Maintenance Test Equipment . 6-1
6-U Checkout and Maintenance Tools . 6-5
6- III List of Operating Procedure JDC's for GSE . 6-6
7- 1 Equipment Required for Checkout . 7-2
7-n PGNCS Interconnect Cables . 7-4
7— III Inertial Subsystem Interconnect Cables . 7-9
7- IV Computer Subsystem Interconnect Cables . 7-14
8- 1 PGNCS and ISS Loop Diagrams and Schematics . 8-4
I-xxvii/I-xxviii
ill
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
LIST OF RELATED MANUALS
-1021038
-1021039
-1021040
ND-1021043
Packing, Shipping and Handling Manual
Auxiliary Ground Support Equipment Manual
Bench Maintenance Ground Support Equipment Manual
Block II Primary Guidance, Navigation, and Control
System Manual
I -xx ix /I- xxx
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
INTRODUCTION
This manual provides information necessary for checkout, maintenance, and re¬
pair of the lunar excursion module (LEM) primary guidance, navigation, and control
system (PGNCS) (figure 1-1). Included in the manual are functional analysis, detailed
theory of operation, component description, system tie-in, and description of flight
operations. The manual also provides for an introduction and complete familiarization
with the PGNCS.
Job Description Cards (JDC's) containing detailed step-by-step procedures are
contained in separate supplementary volumes. Listings of the JDC's required for given
tests and the sequence of performing the JDC's are included in the manual.
This manual and its JDC's cover PGNCS system part number 6015000-011 and shall
be used in the laboratories at Kennedy Space Center, the Manned Spacecraft Center (MSC),
and at Grumman Aircraft Engineering Corporation (GAEC). Portions of this manual
pertaining to the luminous beacon are also applicable for use in the laboratories at
North American Aviation (NAA). Source data available as of 15 January 1966 was used
in preparation of the basic issue of this manual.
This manual is prepared in accordance with E-1087 Documentation Handbook and
National Aeronautics and Space Administration (NASA) contract NAS 9-497, exhibit D.
Appendix A contains a listing of technical terms and abbreviations used in the
manual. Appendix B explains the function and relationship of the System Identification
Data List (SIDL) to the manual. Appendix C will contain the logic symbols used in the
discussion of the computer logic diagrams.
Changes to the manual are requested by sending a completed Technical Data
Change Request (TDCR) form to:
Apollo Field Service Publications, Department 38-01
AC Electronics Division GMC
PLT Ml
Milwaukee, Wisconsin 53201
I-xxxi/l-xxxii
ND-1021042
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM MANUAL
LEM GUIDANCE COMPUTER-
INERTIAL
MEASURING
UNIT.
COUPLING DATA UNIT
POWER AND SERVO
ASSEMBLY
DISPLAY AND
KEYBOARD
OPTICAL
TRACKER
LUMINOUS
BEACON
(LOCATED ON
AN ADAPTER
RING BETWEEN
THE COMMAND
AND SERVICE
MODULE)
SIGNAL CONDITIONER
PULSE
TORQUE ASSEMBLY
I5775B
, l
(R\
Tf )
II l
jjl
\
t - 1
'
t
Figure 1-1. LEM Primary Guidance,
Navigation, and Control System
I-xxxiii/I-xxxiv
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Chapter 1
SYSTEM TIE-IN
1-1 SCOPE
This chapter presents the lunar excursion module (LEM) mission. The chapter
also describes the functional interface between the primary guidance, navigation,
and control system (PGNCS) and the other spacecraft systems.
1-2 LEM MISSION
The purpose of the LEM mission is to transfer the LEM from a circular lunar
orbit into a descent orbit, land two astronauts on the lunar surface, and return them
to the orbiting command and service module (CSM). The LEM mission (figure 1-2),
with respect to the PGNCS, is best described by dividing it into six phases: separation
and transfer orbit insertion, descent coast, powered descent and landing, lunar stay,
launch and powered ascent, and rendezvous and docking.
1-2.1 SEPARATION AND TRANSFER ORBIT INSERTION. Approximately one hour
before the LEM enters the descent orbit, two astronauts leave the CSM and enter
the LEM through the top docking hatch. The crew then checks out the various LEM
systems, establishes a voice link, and, after initial PGNCS turnon, establishes a time
reference for the LEM guidance computer (LGC), and coarse aligns the inertial meas¬
uring unit (IMU) using CSM data. One astronaut then manually commands reaction
control system (RCS) jet firing to separate the LEM from the CSM. The IMU is
fine aligned. Near the end of the second lunar orbit, the LEM descent engine is fired
by the PGNCS and the LEM begins its descent. The timing and duration of LEM descent
engine firing is critical, to insure the proper elliptical Hohmann transfer orbit.
1-2.2 DESCENT COAST. During the descent coast phase, the LEM is in free fall on
an elliptical flight path. During free fall, the astronauts check out the landing radar
(LR). At the perilune of the Hohmann transfer orbit, the LEM is at an altitude of
approximately 50,000 feet and has a velocity vector essentially parallel to the lunar
surface. During this phase, the PGNCS determines the flight parameters required
for powered descent.
1-1
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
CSM
Figure 1-2. LEM Mission Phases
1-2.3 POWERED DESCENT AND LANDING. In preparation for powered descent,
an IMU fine alignment is performed. At the perilune of the descent orbit, the PGNCS
issues a descent engine start discrete. The descent engine firing slows the LEM
which begins the actual descent to the lunar surface. During descent, the PGNCS con¬
trols the engine trim and thrust level, controls the LEM attitude, and provides visual
displays of the guidance system status. During the final approach and landing, the
PGNCS holds the LEM at a constant attitude, allowing the astronaut to view the landing
site. The astronaut can select a new landing site by inserting new landing site coordinates
into the LGC. The LGC will automatically control the RCS and the descent engine to
guide the LEM to the new landing site. Inertially derived flight parameters are up¬
dated in the LGC by comparison with the altitude and velocity parameters determined
from LR measurements.
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
1-2.4 LUNAR STAY. After LEM touchdown the astronauts check out all systems
for damage and insure that the systems can perform the functions required for a
successful ascent. All equipment not required for lunar stay is then turned off. The
astronauts survey the surrounding lunar landscape, secure the hatches, and perform
a final check on the portable life support system (PLSS). After the LEM is secured,
one astronaut, wearing the PLSS, leaves the LEM to explore the lunar surface. The
exploring astronaut inspects the LEM and sets up communication antennas. A television
system sends pictures of the lunar scene to earth. The astronaut always in direct
voice contact with the LEM, explores the lunar surface, makes photographic records,
and collects surface samples. After approximately three hours, the astronaut must
return to replenish his PLSS. Additional surface explorations depend upon the planned
stay time. Near the end of the lunar stay, the PGNCS is brought to an operate con¬
dition and the IMU is coarse and fine aligned. The IMU is fine aligned to a known
reference coordinate system by making star sighting measurements. The LEM optical
device tracks the orbiting CSM and sends data to the LGC which calculates applicable
flight parameters in preparation for the launch and powered ascent.
1-2.5 LAUNCH AND POWERED ASCENT. After the astronauts prepare the LEM,
the PGNCS determines time of launch and ascent trajectory based on a fixed rendezvous
aim point. Mechanical and electrical separation of the two LEM stages takes place
and the LGC issues the ascent engine start discrete at a time calculated to effect a
successful rendezvous.
During powered ascent, the LEM rises vertically and then is pitched to attain
a Hohmann transfer orbit for the rendezvous. Because the ascent engine is a fixed-
position, fixed-thrust engine, the LEM attitude during ascent is controlled by the LGC
which issues commands to the RCS jets. The LGC determines necessary RCS commands
by comparing calculated values with actual flight parameters obtained from the inertial
subsystem (ISS), and determines required attitude changes to correct any differ¬
ences. When the injection of the LEM into the proper elliptical orbit is accomplished,
the LGC issues the ascent engine off discrete and the LEM enters the coasting portion
of the ascent phase.
1-2.6 RENDEZVOUS AND DOCKING. LEM guidance during this phase is a combination
of optical tracking data and inertial data. Azimuth and elevation data from the optical
tracking device and velocity and attitude information from the IMU are used by the
LGC to control the RCS to maintain attitude and to provide a display of position and
velocity information. During rendezvous, the LEM is maintained at an orientation such
that the CSM is visible through the vehicle windows.
Terminal rendezvous maneuvers begin when the LEM and CSM are approximately
five nautical miles apart. The LGC computes the intercept time and with this data
updates the thrust vector and velocity requirements. Three ascent engine bums during
terminal rendezvous reduce the closing rate to near zero. The LGC utilizes the RCS
1-3
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
to maintain vehicle attitude during these burns. The final step is docking, which is
initiated when the vehicles are approximately 500 yards apart. The astronaut uses
the translation controller and attitude controller in a computer-aided manual operation
to guide the LEM to hard docking with the CSM. The two astronauts then leave the
LEM and transfer to the CSM through the vehicle's forward tunnel to prepare for
the return to earth. The LEM is jettisoned following crew transfer to the CSM.
1-3 LEM STRUCTURE
The LEM (figure 1-3) has two stages mated to form one structure: the ascent
stage and the descent stage. These stages and the umbilical interconnecting cables can
be separated at launch from the lunar surface or because of mission abort during
descent.
The approximate LEM external dimensions are shown in figure 1-4. At earth
launch, the weight of the LEM is approximately 30,000 pounds.
1-3.1 ASCENT STAGE. The ascent stage, constructed mainly of aluminum alloy, con¬
sists of the crew compartment, a midsection, aft equipment bay, tankage sections,
associated hatches, and windows.
From the crew compartment, the astronauts control all phases of the LEM mission.
The crew also uses this compartment as their operations center during their lunar
stay.
The displays and controls associated with the PGNCS are located at the front of
the crew compartment. The IMU, a portion of its electronics, and the optical tracking
device are located in an enclosure above the crew compartment. The remaining PGNCS
components are mounted on coldplates to the rear wall of the ascent stage midsection.
The midsection is cylindrical, smaller than the crew compartment, and directly
behind it. The ascent engine and related components are in the midsection, the LEM’s
center of gravity. Also contained in the LEM’s midsection are the ascent engine hatch,
top hatch, environmental control system (ECS), and equipment that requires crew ac¬
cessibility.
To transfer from the CSM to the LEM while in lunar orbit, the crew uses the upper
docking tunnel at the top centerline of the ascent stage. The forward tunnel, at the
lower front of the crew compartment, is used for entering and leaving the LEM while
on the lunar surface.
The aft equipment bay, at the rear of the vehicle, is separated from the mid¬
section by a pres sure -tight bulkhead. This area houses the glycol loop for the ECS,
inverters, batteries, and equipment for the electrical power system (EPS).
1-4
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Figure 1-3. LEM
1-5
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Figure 1-4. LEM External Dimensions
1-6
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The propellant tankage sections are located on either side of the midsection
outside the pressurized area. The tankage sections contain the ascent engine fuel
and oxidizer tanks; RCS fuel, oxidizer, and helium tanks; and ECS water tanks. The
ratio by weight of oxidizer to fuel is 1.6 to 1; therefore, to maintain the lateral center
of gravity on the vehicle X axis, the ascent engine propellant tanks are offset to one
side.
Two triangular windows in the front face of the crew compartment provide visi¬
bility. Each window has approximately 1.6 square feet of viewing area and are canted
down and to the side to increase visibility. Each window consists of two panes.
1-3.2 DESCENT STAGE. The descent stage, constructed mainly of aluminum alloy,
has equipment necessary to land on the lunar surface. It is also a platform for the
launching of the ascent stage after completion of the lunar exploration. The descent
engine is the center of the stage surrounded by its four main propellant tanks. In
addition to the descent engine and its related components, the descent stage houses the
descent control instrumentation; scientific equipment; EPS batteries; and tanks for
water used by the ECS. Landing gear and the LR antenna are attached to the descent
stage.
1-4 LEM SYSTEMS
Functionally, there are seven LEM systems. Four of these systems control
the LEM flight. The PGNCS or the stabilization and control system (SCS) receives
inputs from the crew and electrical inputs from the inertial sensors to generate
commands that result in rotation and translation maneuvers. The RCS or propulsion
system provides external forces and mechanical couples to maneuver the LEM under
the control of the PGNCS or the SCS. The crew obtains information from the LGC
(part of the PGNCS), by communications (Manned Space Flight Network), or displays
that indicate the necessity to initiate one or more of the basic LEM motions. The
three remaining LEM systems are indirectly related to LEM control. They provide
the power (EPS), environmental control (ECS), and the communications [[communi¬
cations and instrumentation system (CIS)].
1-4.1 PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM. The PGNCS
provides the measuring and data processing capabilities and control functions nec¬
essary to accomplish the LEM mission. The PGNCS utilizes inertial components for
guidance, an optical device for navigation, and a digital computer for data processing
and issuance of flight control signals.
The inertial guidance portion of the PGNCS, the IMU, employs accelerometers
mounted on a gyroscopically stabilized gimbal-mounted platform. The IMU senses
acceleration and attitude changes instantaneously and provides signals to a digital com¬
puter, the LGC, for the generation of attitude control and thrust commands.
For navigation, the PGNCS utilizes an optical tracking device to take star sight¬
ings and obtain measurements. These sightings are used by the LGC to establish
proper alignment of the stable platform. The LGC contains a catalog of celestial
1-7
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
bodies and is programmed to calculate alignment commands using the information
obtained from the optical sightings. In addition to functioning as a data processing
unit, the LGC, through its flight programs, performs the function of a digital auto¬
pilot in controlling the LEM.
1-4.2 STABILIZATION AND CONTROL SYSTEM. The SCS consists of two major
sections: the control electronics section (CES) and the abort guidance section (AGS).
The CES processes flight control signals during all mission phases. The AGS pro¬
vides the CES automatic steering commands, derived from explicit guidance equa¬
tions, in the event of mission abort due to a PGNCS malfunction.
The CES consists of an attitude and translation control assembly (ATCA), a descent
engine control assembly (DEC A), rate gyro assembly (RGA), two translation con¬
troller assemblies (TCA), and two attitude controller assemblies (AC A). The CES
processes and routes signals to fire any combination of the 16 thrusters in the RCS to
control LEM attitude and translation. The attitude and translational control inputs
originate from any of three sources: the PGNCS during normal automatic operation,
the AC A and TCA during manual operations, or the AGS during an abort.
The CES converts the applicable input commands into pulsed or constant level
signals and routes them to the RCS to fire the appropriate thrusters. Rate signals
from the CES are displayed on the flight director attitude indicator (FDAI).
The CES also processes '’ON-OFF'* commands for the ascent and descent engines,
and routes automatic and manual throttle commands to the descent engine. Trim
control of the descent engine insures that the thrust vector operates through the
vehicle center of gravity.
The AGS provides abort capability from any point in powered descent or powered
ascent and increases crew safety by acting as a backup system to the PGNCS. The
AGS has three main assemblies: abort sensor assembly, abort electronics assembly,
and data entry and display assembly.
The abort sensor assembly utilizes a strap-down technique employing three single-
degree-of-freedom integrating rate gyros and three accelerometers. This backup
guidance provides vehicle attitude, angular velocity, and translational acceleration
indications. The outputs of the abort sensor assembly go to the abort electronics
assembly, a 4,096 word capacity general purpose computer. Computations are performed
using the inputs from the abort sensor assembly. When the AGS is in control of the
LEM, the results are displayed and control signals are issued to the vehicle's reaction
control and propulsion systems.
The abort sensor assembly measures the accelerometer triad rotation from, and
resolves the acceleration into, a fixed reference frame. This reference frame is
provided by an initial alignment of the AGS with the PGNCS. Initial alignment is
required for attitude, velocity, time, and position. Velocity and position vectors are
manually entered into the computer by a data entry device available to the astronaut.
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Attitude alignment is accomplished by transferring PGNCS IMU gimbal angles to the
computer. The abort electronics assembly receives this data from the coupling data
unit (CDU) in the same manner and at the same time as the LGC (i.e. incremental
angles accumulated from a zero reference after "CDU ZERO").
1-4.3 PROPULSION SYSTEM. The LEM utilizes separate, complete, and independent
descent and ascent propulsion systems, which consist basically of a liquid propellant
rocket engine and its propellant storage, pressurization, and feed components.
The descent propulsion system is in the LEM descent stage and utilizes a throttle-
controlled, gimbaled engine. The engine injects the LEM into the descent transfer orbit
and is used during powered descent and landing to control the rate of descent. The
descent engine, developing 10,500 pounds maximum thrust in a vacuum at full throttle
and 1,050 pounds minimum thrust, can be gimbaled 6 degrees in any direction. The
PGNCS issues the "ON-OFF" commands for the descent engine and also provides sig¬
nals controlling thrust magnitude and gimbal trim position.
The propellant used in both propulsion systems is a 50-50 fuel mixture of hydrazine
and unsymmetrical dimethylhydrazine using nitrogen tetroxide as the oxidizer and he¬
lium as the tank pressurant.
The ascent propulsion system utilizes a fixed, constant-thrust engine installed
along the centerline of the ascent stage midsection and includes the associated pro¬
pellant feed tanks and pressurization components. The engine develops 3,500 pounds
thrust in a vacuum, sufficient to launch the ascent stage from the lunar surface and place
it in orbit. The PGNCS issues the "ON-OFF" commands for the ascent engine.
1-4.4 REACTION CONTROL SYSTEM. The RCS provides rocket thrust impulses that
stabilize the LEM during descent and ascent and control the LEM attitude and trans¬
lation about or along all axes. The RCS has 16 thrust chambers supplied by two separate
and independent propellant feed and pressurization sections. The thrust chambers
are mounted in clusters of four on outriggers equally spaced around the LEM ascent
stage. In each cluster, two thrust chambers are mounted on a vertical axis, facing
in opposite directions; the other two are spaced 90 degrees apart, parallel to the
LEM's Y and Z axes. The RCS utilizes the same fuel as the ascent engine. In the event
of RCS fuel depletion, the remaining ascent fuel can be used for the RCS. The RCS
can be operated in any of three modes: manual, automatic, or semi-automatic. The
PGNCS supplies "ON-OFF" signals through the SCS to the valves on the desired thrust
chambers during the automatic or semi-automatic mode. The automatic mode is
normally used to provide attitude control during all mission phases except when manual
control is required. It is possible to select manual control in one or two axes and retain
automatic control in the other axis during all mission phases. The semiautomatic
mode combines automatic attitude hold control with manual control. The LEM attitude
is changeable about each axis using the astronaut’s attitude controller. This mode is
used primarily to control the LEM during the rendezvous and docking phase of the
mission. In the manual mode, all control commands originate from the attitude con¬
troller, including manual control of the thrust duration.
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All automatic translational commands originate in the PGNCS and are routed to
the RCS similar to the attitude control signals.
1-4.5 ELECTRICAL POWER SYSTEM. The EPS provides 28 vdc and 115 vac, 400 cps
power to the PQNCS. This power originates from six batteries, four in the descent
stage, and two in the ascent stage. The batteries, the silver-zinc type, are rated at
80 watts per hour per pound of weight. The 115 vac, 400 cps power is obtained by
routing the 28 vdc through an inverter.
1-4.6 ENVIRONMENTAL CONTROL SYSTEM. The ECS sustains life in space by
providing breathable atmosphere, acceptable temperatures, food and water, and waste
disposal. In addition, the ECS circulates an ethylene glycol-water coolant about the
temperature sensitive electronic equipment in the PGNCS and other LEM systems to
provide thermal stability. The IMU has coolant circulated through its case while the
power and servo assembly (PSA), pulse torque assembly (PTA), signal conditioner,
LGC and CDU are mounted on coldplates through which the coolant is circulated to
provide temperature control.
1-4.7 COMMUNICATIONS AND INSTRUMENTATION SYSTEM. The CIS links the lunar
astronauts, the orbiting CSM, and earth monitoring stations.
The communications portion contains two radio frequency (RF) sections, one oper¬
ating in the VHF range and the other in the UHF range; a television section; and a signal
processing section. In addition to two-way voice communication, the RF section re¬
ceives and transmits tracking and range information, biomedical information, and
emergency code keying in the event of voice transmission failure. The television sec¬
tion is used by the extravehicular astronaut to televise the lunar surface within an
eighty foot radius of the grounded LEM. In the signal processing section, critical signals
of the PGNCS are conditioned and supplied to pulse code modulated (PCM) telemetry
equipment for transmission to earth. Telemetry data can be stored when direct com¬
munication with the earth is not possible.
The instrumentation portion provides the astronauts and ground facilities with LEM
performance data during the mission by sensing physical status data, monitoring the
various systems, and performing inflight and lunar surface checkout. This system also
contains the scientific instruments which are used by the astronauts during their lunar
stay.
1-5 PGNCS INTERFACE
PGNCS operation during the LEM mission requires the interface of the PGNCS
with the other LEM systems, the displays and controls on the crew display and con¬
trol panels, the landing radar, and the astronauts. The functional interface of the
PGNCS is shown in figure 1-5.
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Figure 1-5. LEM PGNCS Functional Interface, Block Diagram
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1-5.1 SYSTEMS. Four LEM systems (SCS, ECS, CIS, and EPS) have direct interface
with the PGNCS and two systems (propulsion system and RCS) have indirect inter¬
face with the PGNCS. The indirect interface of the propulsion system and the RCS
occurs through the SCS. These two systems may thus be controlled by the PGNCS or
by the backup control provided by the AGS of the SCS. Descriptions and sources
of the SCS interface signals are provided in table 1-1. Descriptions of the interfaces
with the other systems are provided in paragraph 1-4.
1-5.2 DISPLAYS AND CONTROLS. Several displays and controls located on the crew
control panels, LGC display and keyboard (DSKY) panel, and the SCS control panel
interface with the PGNCS. Two sets of hand controllers are provided for manual
control of the LEM and interface with the PGNCS. Descriptions of the displays and
controls are in table 1-IL
1-5.3 LANDING RADAR. The landing radar (LR) provides data to the LGC from which
LEM velocity (in antenna coordinates) and LEM altitude may be determined. The
data is also available for visual display, independent of the PGNCS, except that the
velocity is in spacecraft coordinates.
The landing radar which operates in the X-band, consists of an antenna assembly,
a solid-state electronics assembly, and a control panel. Velocity data is acquired
from a three beam continuous wave Doppler radar. Altitude data is provided by a
one beam FM continuous wave radar altimeter. The antenna assembly accommodates
the requirements of both the Doppler and the altimeter beams.
Landing radar and PGNCS interface include digital data transfer, scaling, velocity
and range sensing, status, and antenna positioning. Descriptions and sources of the
interface signals are in table 1-in.
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Table 1-1. SCS Interface Signals
Signal Name
Source
Description
Manual translation
commands (±x, ±y,
±z)
SCS
Signals from translation controller which
fire RCS jets by LGC control.
Attitude control out
of detent
SCS
Signal from attitude controller indicating
that it is not in neutral position.
Rate of descent (±)
SCS
Discretes commanding an increase or
decrease in rate of descent.
Gimbal off (pitch,
roll)
SCS
Signal to LGC indicating that descent
engine pitch or roll gimbal is off null.
Trim commands
(± pitch, ± roll)
LGC
Signals which control trim of descent
engine.
Engine on-off
LGC
Signal to turn descent or ascent engine on
or off.
Descent engine
throttle command
(decrease, increase)
LGC
Signal to increase or decrease thrust of
descent engine.
RCS jets on-off
LGC
Signals (16) to turn RCS jets on or off.
Increments of IMU
gimbal angles
(±Z*0IG, ±A9mg»
±^-0OG
LGC
Supplies changes in IMU gimbal angles
to AGS.
CDU zero (initial
clear)
LGC
Sets alignment logic of AGS to zero.
800 cps ±1%
PGNCS
Provides reference between PGNCS and
SCS.
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Table 1-n. Displays and Controls
Display or Control
Function
GUID CONT switch
Selects either primary guidance (PGNS) or abort
guidance (AGS). Normally in the PGNS position.
MODE SEL selector
Three position switch used during landing phase to
select one of three inputs to be displayed on AZ
RT/ELEV RT-LAT VEL/FWD VEL indicator.
Inputs are landing radar (LDG RADAR), PGNS and
AGS.
RNG/ALT MON switch
Controls display of RANGE/RANGE RATE- ALT/
ALT RATE indicator. Positions are RNG/RNG RT
and ALT/ALT RT.
RATE/ERR MONITOR
switch (2)
Selects one of two inputs for AZ RT/ELEV RT-LAT
VEL/FWD VEL indicator and attitude needles of
FDAI.
ATTITUDE MON
switch (2)
Selects one of two inputs to FDAI total attitude dis¬
play and attitude error needles during landing.
THR CONT switch
Selects either automatic (AUTO) or manual (MAN)
control of descent engine throttle. Normally in
AUTO position.
MAN THROT switch
Activates either commander’s (CDR) or system
engineer's (SE) translation controller for manual
throttling of descent engine.
ABORT
Pushbutton to cause mission abort at any point be¬
tween LEM/CSM separation and touchdown on lunar
surface with descent stage still attached.
ABORT STAGE
Pushbutton to cause mission abort using ascent
stage.
AZ RT/ELEV RT-
LAT VEL/FWD
VEL meter (2)
Provides visual displays of vehicle forward and
lateral velocity during landing.
(Sheet 1 of 2)
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Table l-II. Displays and Controls
Display or Control
Function
RANGE/RANGE
RATE- ALT/ALT
RATE meter
Provides visual displays of range, altitude, range
rate, and altitude rate.
FDAI meter (2)
Provides three visual displays, total attitude, atti¬
tude error, and attitude change rate. PGNCS or
AGS provides inputs for total attitude and attitude
error. Attitude rate signals are provided by SCS
rate gyros.
LGC and ISS warning
indicators, PGNS
caution indicator.
Controlled by instrumentation system which re¬
ceives discretes from LGC when certain PGNCS
troubles exist.
MODE CONTROL
selector
A three-position selector located on SCS control
panel concerned with attitude control. Positions
are OFF, ATT HOLD, and AUTO. In AUTO posi¬
tion, fully automatic attitude control is achieved
through PGNCS or AGS control of RCS jets. ATT
HOLD position allows crew to manually reposition
LEM and have new position automatically maintained
by LGC.
IMU CAGE switch
Switch located on DSKY mounting panel to drive
IMU gimbal angles to zero.
Attitude controller (2)
Three-axis, pistol-grip, right-hand device for
manual attitude control of LEM. Outputs from
controller are processed by PGNCS or may be
routed directly to RCS.
Translation controller
(2)
Three-axis, T-handle, left-hand device for manual
translation control of LEM. Using switch located
next to T-handle, controller can operate RCS jets
or throttle the descent engine.
(Sheet 2 of 2)
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Table 1-ID. Description of Landing Radar Interface Signals
Signal Name
Source
Description
Antenna positioning
command
DSKY
and
LGC
Changes antenna position.
Antenna position
#1 (descent)
LR
Indicates to LGC that antenna is in posi¬
tion #1.
Antenna position
#2 (hover)
LR
Indicates to LGC that antenna is in posi¬
tion #2.
Velocity data good
LR
Indicates to LGC that LR velocity
trackers have locked on.
Range data good
LR
Indicates to LGC that LR range trackers
have locked on.
Range low scale
factor
LR
Indicates to LGC that a change in scale
factor is necessary. Issued automat¬
ically at approximately 2,500 feet.
LR in "0" and LR
in "l"
LR
Digital pulses sent to LGC which contain
range and velocity data.
Readout command
LGC
Indicates that LGC is ready to receive
LR data pulses.
Gate reset
LGC
3,200 cps continuous LGC output to reset
LR transfer gates.
Range strobe
LGC
Timing pulses to enable LR transfer
gates.
vxa» Vya, VZa
strobe pulses
LGC
Timing pulses to enable LR transfer
gates.
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Chapter 2
SYSTEM AND SUBSYSTEM FUNCTIONAL ANALYSIS
2-1 SCOPE
This chapter provides functional descriptions of the PGNCS and its subsystems.
This chapter describes how the PGNCS subsystems perform the PGNCS operations.
2-2 PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM.
The PGNCS is functionally divided into three major subsystems: inertial, optical,
and computer. The PGNCS performs three basic functions: inertial guidance, navigation,
and autopilot stabilization and control. Within these functions the subsystems, or
combination of subsystems, with assistance from the astronaut, perform the following
operations:
(1) Establish an inertial reference which is used for measurements and compu¬
tations.
(2) Aligns the inertial reference by optical measurements and, through inter¬
face, aligns the inertial reference with the CSM PGNCS.
(3) Calculates the position and velocity of the LEM by inertial navigation.
(4) Accomplishes a LEM and CSM rendezvous by optical navigation and inertial
guidance.
(5) Generate attitude control and thrust commands to maintain the LEM on a satis¬
factory trajectory.
(6) Control throttling of descent engine during lunar landing.
(7) Display pertinent data related to guidance status.
(8) Controls ascent engine burn time to obtain proper velocity for rendezvous orbit.
To perform its inertial guidance functions, the PGNCS employs an IMU containing
accelerometers mounted on a gyro stabilized, gimbal-mounted platform. The IMU,
three channels of the CDU, the pulse torque assembly (PTA), and the PSA form the ISS
of the PGNCS.
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To perform its navigation functions, the PGNCS employs the LEM optical rendez¬
vous subsystem (LORS), which consists of an optical tracker located on the LEM
and a luminous beacon located on the CSM. During the powered descent and landing
phase, the PGNCS receives altitude and velocity data from the LR, which is used to
update or check inertially derived data.
The LGC is a digital computer which serves as both the control element and the
primary data processing element of the PGNCS. The LGC and the display and key¬
board (DSKY) form the computer subsystem of the PGNCS.
Figure 2-1 illustrates the signalflow and interface between the three PGNCS sub¬
systems.
2-3 LEM AND PGNCS AXES
Several sets of axes are associated with the LEM and PGNCS. Figure 2-2 illustrates
these various orthogonal sets which are defined in the following paragraphs. Positive
rotation about each axis is as defined by the right hand rule.
2-3.1 LEM SPACECRAFT AXES. The LEM spacecraft axes provide a reference for all
other sets of axes and define the point about which attitude maneuvers are performed.
The LEM spacecraft axes, designated XleM, YleM. ZleM. are referred to as the
yaw, pitch, and roll axes respectively. The Xj_,EM axis points through the upper dock¬
ing hatch and the ZleM axis points through the forward hatch. The YleM axis is
perpendicular to the XleM and the ZleM axes and can be considered to be pointing
out of the astronaut’s right shoulder as he faces toward the forward portion of the LEM.
2-3.2 NAVIGATION BASE AXES. The navigation base provides a precise alignment of
the IMU to the optical tracker and a means of attaching both units to the spacecraft.
The navigation base is mounted to the LEM structure so that a coordinate reference
system is formed by its mounting points. The Yj^b axis is defined by the centers
of the two upper mounting points and is parallel to the YleM axis. The Xjsjg axis is
defined by a line through the center of the lower mounting point, perpendicular to the
yNB axis and parallel to the Xlem axis. The Zjyjg axis is mutually perpendicular to the
Xnb and ynb axes and is parallel to the Zlem axis.
2-3.3 INERTIAL AXES. The inertial axes provide references for measuring changes in
velocity and attitude. At zero degree, the inertial axes are parallel to the navigation
base axes.
2-3. 3.1 Gimbal Axes. The gimbal axes (outer, middle, and inner) are the axes of the
movable gimbals. The axes are defined by the intergimbal assemblies which provide
each gimbal with rotational freedom. The attitude of the spacecraft with respect to
the stable member is measured by the gimbal resolvers located in the intergimbal
assemblies.
2-3. 3. 2 Stable Member Axes. The stable member axes (Xsm» Ysm. Zsm) provide
a reference for aligning the inertial components and for defining the angular orientation
of the inertial axes during flight.
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Figure 2-1. PGNCS Subsystems Interface, Block Diagram
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OPTICAL TRACKER
AZIMUTH AXIS
Figure 2-2. LEM and PGNCS Axes
2-3. 3. 3 Accelerometer Axes. The accelerometer axes (Xa, Ya, Za) are the positive
input axes of the accelerometers and are parallel to the stable member axes. Velocity
changes are measured along the accelerometer input axes. This velocity data is used
to determine spacecraft position and velocity.
2- 3.3. 4 Gyro Axes. The gyro axes (Xg, Y~, Z_) are the positive input axes of the
stabilization gyros and are parallel to the stable member axes. If the attitude of the
stable member is changed with respect to inertial space, the gyro senses the change
about its input axis and provides an error signal to a servo loop which realigns the
stable member to its original orientation.
2-4 INERTIAL SUBSYSTEM
The ISS performs three major functions. It measures changes in LEM attitude,
assists in generating steering commands, and measures spacecraft velocity due to
thrust. To accomplish these functions, the IMU provides an inertial reference consisting
of a stable member with a three degree of freedom gimbal system and stabilized by
2-4
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three rate integrating gyros. Each time the inertial subsystem is energized, the stable
member must be aligned with respect to a predetermined reference. During flight and
prior to launch from the lunar surface, this alignment is accomplished by sighting
the optical instrument on celestial objects.
Once the ISS is energized and aligned, any rotational motion of the LEM will be
about the stable member, which remains fixed in space. Resolvers mounted on the
gimbal axes act as angular sensing devices and measure the attitude of the LEM
with respect to the stable member. These angular measurements are displayed by the
FDAI and angular changes are sent to the LGC via the CDU.
The desired LEM attitude is calculated in the LGC and compared with the actual
gimbal angles. Any difference between the actual and calculated angles results in the
generation of attitude error signals by the ISS Chanels of the CDU which are sent to
the FDAI for display.
Vehicle acceleration is sensed by three pendulous accelerometers mounted on the
stable member with their input axes orthogonal. The signals from the accelerometers
are supplied to the LGC which calculates the total vehicle velocity.
The modes of operation of the inertial subsystem can be initiated automatically by
the LGC or by the astronaut selecting computer programs through the DSKY. The
status or mode of operation is displayed on the DSKY.
For pruposes of explanation and description, the ISS is divided into functional blocks
as shown in figure 2-3 and described in the following paragraphs.
2-4.1 STABILIZATION LOOP. The three stabilization loops (figure 2-4) maintain the
stable member in a specific spatial orientation so that three mutually perpendicular 16
pulsed integrating pendulum (16 PIP) accelerometers can measure the proper compo¬
nents of LEM acceleration with respect to the coordinate system established by the
stable member orientation. An input to the stabilization loops is created by any change
in LEM attitude with respect to the spatial’ orientation of the stable member. With near
zero gimbal angles, the inertia of the stable member tends to maintain the stable mem¬
ber in a fixed spatial orientation. Because of gimbal friction and unbalances, motion of
the LEM structure relative to the stable member will produce a torque on the stable
member which will tend to change its orientation. This change is sensed by the stabil¬
ization gyros. When the gyros sense an input, they issue error signals which are
amplified, resolved, if necessary, into appropriate components, and applied to the
gimbal torque motors. The gimbal torque motors then drive the gimbals until the stable
member regains its original spatial orientation.
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Figure 2-4. Stabilization Loop, Block Diagram
The stabilization loop consists of three pre-aligned Apollo II inertial reference
integrating gyro (Apollo n IRIG) assemblies, a gyro error resolver, three gimbal servo
amplifiers, three gimbal torque motors, three gimbals, and circuitry associated with
these components. The inner gimbal is the stable member upon which the three stabili¬
zation gyros are mounted. The gyros are mounted with their input axes oriented in an
orthogonal configuration. Movement of any gimbal tends to result in a movement of the
stable member and rotation about the input axes of one or more of the stabilization
gyros.
The stabilization loop contains three parallel channels. Each channel starts with
a stabilization gyro (X, Y, or Z) and terminates in a gimbal torque motor. The torque
motor drives the gimbals resulting in a movement of the stable member and a movement
of the stabilization gyros. When a movement of the IMU support gimbal attempts to
displace the stable member from its erected position, one or more of the stabilization
gyros senses the movement and issues error signals. The phase and magnitude of the
3, 200 cps gyro error signal represents the direction and amount of rotation exper¬
ienced by the gyro about its input axis. The error signal is fed from the gyro signal
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generator ducosyn to the associated IRIG preamplifier, which is a part of the prealigned
Apollo II IRIG assembly. Amplification of the error signal is required to achieve a high
signal- to-noise ratio through the gimbal slip rings.
The amplified gyro error signals also represent motion of the stable member about
its axis since the stable member axes (Xsm» Ysm» zSM)andthe gyro axes (X g, Yg, Zg)
are parallel to one another. * If the middle and outer gimbal axes remain parallel with
the stable member axes, then movement of the outer gimbal (a yaw movement of the
LEM) is sensed by only the X gyro and movement of the middle gimbal (roll move¬
ment of the LEM) is sensed by only the Z gyro. Movement of the stable member
about the inner gimbal axis (Ysm)> however, changes the relationship of the X and Z
gyro input axes to the outer and middle gimbal axes. As a result, a movement of the
middle or the outer gimbal is sensed by both X and Z gyros. The input required by the
gimbal servo amplifiers to drive the gimbals and move the stable member back to its
original position must be composed of components of both the X and Z gyros. The re¬
quired gimbal error signals are developed by the gyro error resolver. The gyro error
signals, E(Xg) andE(Zg), are applied to the stator windings of the gyro error resolver.
The rotor windings are connected to the inputs of the outer and middle gimbal servo
amplifiers. Movement of the stable member about the inner gimbal axis (pitch move¬
ment of the LEM) changes the position of the resolver rotor relative to the resolver
stator. This change corresponds electromagnetically to the change in the relationship
of the stable member axes to the outer and middle gimbal axes. The outputs taken from
the rotor are the required middle and outer gimbal error signals (Emg and E0g). Since
the inner gimbal torque motor axis and the Y axis of the stable member are the same
axis, the Y gyro error signal, E(Yg), is equal to the inner gimbal error signal, (Ejg),
and is fed directly to the inner gimbal servo amplifier.
The three identical gimbal servo amplifier modules are located in the PSA and
contain a phase sensitive demodulator, a filter, and a dc operational power amplifier.
The phase sensitive demodulator converts either the 3, 200 cps gimbal error or 800 cps
coarse align error, zero or pi phase, signals into a representative positive or negative
dc signal. Thedc signal is filtered and applied to a dc operational amplifier with current
feedback. The compensation network in the feedback circuit of the amplifier controls
the response characteristics of the entire stabilization loop. The output of the dc
amplifier has an operating range between +28 vdc and -28 vdc and drives the respec¬
tive gimbal torque motor directly in either angular direction.
The gain required for each stabilization loop differs. This difference compensates
for the differences in gimbal inertia. The proper gain is selected by the connections to
the gimbal servo amplifier module. A single torque motor is mounted on each gimbal at
the positive end of the gimbal axis. The torque motors drive the gimbals to complete
the stabilization loop.
* The Z gyro has its positive input axis aligned to the -ZgM axis but this is compensated
for by reversing the polarity of the 3,200 cps excitation to the primary winding of the Z
gyro signal generator ducosyn which causes the Z gyro error signal to be representative
of the direction and amount of motion about the Zsm axis.
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The orientation of the stable member can be changed in either the coarse align, fine
align, or IMU cage modes. Signals to reposition the gimbals are injected into the gimbal
servo amplifiers from the CDU during the coarse align and IMU cage modes and into
the stabilization gyros from the fine align electronics during the fine align mode. During
the IMU cage mode and the coarse align mode, the reference signal for the demodulator
in the gimbal servo amplifier is externally switched from 3, 200 cps to 800 cps.
2-4,2 FINE ALIGN ELECTRONICS. The fine align electronics (figure 2-5) provides
torquing current to the stabilization gyros to change the orientation of the IMU gimbals
during the fine align mode. The operation of the fine align electronics is controlled by
the LGC.
The components of the fine align electronics are common to the three stabilization
gyros. The fine align electronics provides torquing signals to the stabilization gyros
one at a time on a time shared basis. The fine align electronics consists of a gyro
calibration module, a binary current switch module, and a dc differential amplifier
and precision voltage reference module, all located in the PTA.
151900
Figure 2-5, Fine Align Electronics - Computer Inputs
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The fine align electronics is enabled and controlled by LGC inputs to the gyro cal¬
ibration module. The LGC inputs consist of torque enable pulses, gyro select pulses,
a torque set command, and a torque reset command. The fine align electronics is en¬
abled by the torque enable pulses. The torque enable pulses are a train of pulses
three microseconds in width and occurring at 102.4 kpps. The torque enable pulses
are applied through a relay driver to energize the torque enable relay in the cali¬
bration module. When the torque enable relay is energized, system 28 vdc is applied
to the precision voltage reference (PVR) and regulated 120 vdc from the pulse torque
power supply is applied to the dc differential amplifier and the binary current switch.
The torque enable pulse train is received 20 milliseconds prior to any gyro set
command.
The gyro to be torqued and the direction it is to be torqued is selected by the LGC
by sending gyro select pulses to one of the six +A0or -A 6 inputs. (See figure 2-6. ) The
gyro select pulse consists of a train of pulses three microseconds in width and occur-
ringat 102.4 kpps. The pulse train activates a transistor switch network which controls
current through the T+ or T- coils of the torque generator ducosyn in the gyro selected.
The gyro select pulse train is received 312.5 microseconds (one LGC clock time at
3, 200 pps) prior to any torque set command.
@ ♦ A0Z
I5I89C
Figure 2-6. Fine Align Electronics - Gyro Selection
2-10
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
The torque set and reset commands are 3, 200 pps pulse trains containing pulses
that are three microseconds in width. A 3, 200 pps pulse train will be present on the
torque set line when any gyro is to be torqued. A 3,200 pps pulse train is present on
the torque reset line at all other times. This ensures that the binary current switch is
in the reset condition prior to receipt of a torque enable command from the LGC. When
the gyro has been torqued the proper amount, a torque reset command is issued which
causes the torque current to be cut off. The gyro select pulse train will be removed
312.5 microseconds after the torque reset command has been issued. The torque set
and torque reset pulses are fed through a 1:2 step-up transformer in the calibration
module to the set and reset inputs of the binary current switch.
The torque current from the binary current switch is applied through a tuned re¬
sistive-capacitive compensation network in the calibration module to make the torque
generator ducosyn windings appear as a pure resistive load to the binary current switch.
The torque current to the gyros is via the T±(common) line. Current will flow only
through the selected torque generator coils, the current monitor resistor, and the
scale factor resistor. The voltage drop developed across the scale factor resistor is
used as a feedback to the differential amplifier to regulate the torquing current. The
voltage drop across the current monitor resistor is applied to PTA test points for ex¬
ternal monitoring of gyro torque current.
When no gyro is being torqued, the binary current switch provides current flow
through a dummy load resistor and through the current monitor and scale factor resis¬
tors. In this manner, the binary current switch maintains a continuous ilow of torque
current. The dummy load resistor simulates the impedance of the torque generator
coil and a compensation network.
The torque set and torque reset pulses trigger a flip-flop (bi-stable multivibrator)
in the binary current switch (figure 2-7). If the flip-flop is in the +set condition,
the +set condition will remain until a reset command resets the flip-flop. The out¬
puts of the flip-flop control two transistor switches. If the flip-flop is in the +set
condition, the +set output is present at the base of the +torque current switch, causing
the switch to turn on. The +torque current switch closes the path from the 120 volt
supply through the current regulator to the proper T+ or T- winding of the selected
gyro via the calibration module. If the flip-flop is in the -set condition, the -torque
current switch will turn on and close the current path through the dummy load resistor.
The binary current switch used in the fine align electronics is identical to the
one used in the accelerometer loops. The portion of the binary current switch used
only for the accelerometer loops is disabled in the fine align electronics application.
In the accelerometer loop application, current to the accelerometer T+ torque genera¬
tor coil is provided by the +torque current switch and current to the T- torque genera¬
tor coil is provided by the -torque current switch. Therefore, the +torque and -torque
designations of the switches have significance. In the fine align electronics application
the switch designations have no significance since current to both the T+ and T- coils
of the gyro torque generators is provided by the +torque current switch while the -torque
current switch provides only the dummy load current.
2-11
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
(OUTPUT FOP
PI PA LOOPS ONLY)
POSITIVE
VELOCITY
PULSE (P)
ISI80B
Figure 2-7. Binary Current Switch
The dc differential amplifier and PVR module (figure 2-8) maintains the cur¬
rent through the windings of the torque generator ducosyn at 84 milliamperes. The
PVR is supplied with regulated 28 vdc and, through the use of zener diode circuits,
develops an accurate 6 vdc for use as a reference voltage. The scale factor resistor in
the calibration module also has 6 volts developed across it when 84 milliamperes of cur¬
rent flows through it. A comparison is made by the dc differential amplifier of the PVR
6 volts and the scale factor resistor 6 volts. Any deviation from the nominal 84 milli¬
amperes of torquing current will increase or decrease the voltage developed across
the scale factor resistor and cause an output error signal from the dc differential ampli¬
fier. This error signal controls the current regulator in the binary current switch.
The current regulator, which is in series with the torque generator coils of the selected
gyro and the 120 vdc source, will maintain the torquing current at 84 milliamperes.
2-12
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MANUAL
I5I7SA
Figure 2-8. DC Differential Amplifier and Precision Voltage Reference
The current flow through the windings of the torque generator ducosyn causes the
gyro float to rotate about the gyro's output axis. A + A 6 gyro select command from the
LGC will allow torque current to flow through a T- torque generator coil which results
in a positive rotation of the gyro float about the output axis. A - A 6 gyro select command
produces a negative float rotation. * Float rotation results in an error output from the
signal generator ducosyn. The error signal is applied to the stabilization loop to re¬
position the gimbals and the stable member. The change in gimbal angles is transmitted
by the CDU read counters to the LGC.
* The positive input axis of the Z gyro is aligned to the -ZgM axis but this is com¬
pensated for by reversing the T+ and T- connections to the Z gyro torque generator
ducosyn. A + A0Z gyro select command from LGC will cause a negative float rotation
but since the polarity of the Z gyro signal generator is also reversed the gyro error
signal will appear to represent a positive float rotation. The stabilization loops will
then drive the gimbals in the desired direction.
2-13
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-4.3 ACCELEROMETER LOOP. The three accelerometer loops measure the acceler¬
ation of the stable member along three mutually perpendicular axes and integrate this
data to determine velocity. The velocity is used by the LGC to determine the LEM
velocity vector. Figure 2-9 is a functional diagram of an accelerometer loop.
The three accelerometer loops contain three prealigned 16 PIP assemblies, three
PIP preamplifiers, three ac differential amplifier and interrogator modules, three
binary current switches, three calibration modules, three dc differential amplifier and
precision voltage reference modules, a pulse torque isolation transformer, and asso¬
ciated electronics.
The three mutually perpendicular PIP’s are acceleration sensitive devices. When
fixed in its associated accelerometer loop, the PIP becomes an integrating accelerom¬
eter. The PIP is basically a pendulum-type device consisting of a cylinder with a pen¬
dulous mass unbalance (pendulous float) pivoted with respect to a case. The axis of the
pivots defines the PIP output axis. A signal generator is located at the positive end of
the output axis to provide electrical output signals indicative of the rotational position
of the float. A torque generator located at the other end of the float acts as a trans¬
ducer to convert electrical signals into mechanical torque about the float shaft. The
accelerometer loop using a PIP is mechanized to operate in a binary (two state) mode.
In the binary mode, the PIP pendulum is continually kept in an oscillatory motion.
Thus the two states: positive rotation or negative rotation. The rotation is accom¬
plished by continuously routing torquing current through the torque generator plus or
minus windings.
I3I77A
Figure 2-9. Accelerometer Loop
2-14
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The torque generator has two windings, one to produce torque (rotation) in a positive
direction, the other to produce torque (rotation) in a negative direction. Only one
winding will have current in it at anyone time. The torque winding selection is accom¬
plished by the setting of a flip-flop in the binary current switch (figure 2-7). When the
loop is first energized, the interrogator sets the flip-flop to route the torquing current
to one of the windings, which will rotate the float to null. As the float passes through
null, the phase of the output signal of the signal generator changes, which causes the
interrogator to issue pulses to reset the flip-flop in the binary current switch and thus
route torquing current to the other torque winding. The float is then torqued in the
opposite direction until the signal generator output again changes phase as the float
passes through null which reinstates the cycle.
The output of the signal generator, after being amplified by the PIP preamplifier
is interrogated 3200 times a second by the interrogate pulse. The binary current
switch flip-flop can be reset only when the interrogate pulse is present and the signal
generator output is of the proper phase.
The PIP pendulum motion is an oscillatory motion about its null point and can be
measured in cycles per second. As is characteristic of every electro-mechanical loop,
there exists some natural resonant frequency. The natural frequency is dependent upon
float damping, signal and torque generator sensitivities, and other loop characteristics.
In the case of the accelerometer loop this natural frequency is approximately 500 cps,
and the pendulum oscillates at a frequency close to that. At a torque winding selection
rate of 3200 pulses per second, the value of this frequency can be any value equal to
3200 -J- x where x is any even number.
Using the above ratio, it is possible for the pendulum to have a maximum frequency
of 1600 cps (x equals 2). A frequency of 1600 cps means that for every torque selec¬
tion pulse, the torque current would be routed to the opposite torque generator winding.
Solving the equation f = 3200 x, the frequency closest to 500 is 533-1/3. In this
case; the value of x is six. Thus one complete pendulum cycle will occur during six
torque selection pulses. Dividing the time for the six pulses into positive and negative
rotations, it is seen that the PIP functions in a 3-3 mode (positive rotation for three
torque selection pulses, negative rotation for three torque selection pulses).
The physical configuration of the PIP is such that the float, when moding in its
3-3 state and sensing no acceleration, rotates an equal angular distance on both sides
of an electrical and mechanical null.
The2voltrms, 3200 cps, one phase signal generator excitation voltage is synchro¬
nized with the LGC clock. The signal generator has a center tapped secondary winding
which provides a double ended output, one side having a zero phase reference with re¬
spect to the 3,200 cps excitation and the other side a pi phase reference. The center
tap is connected to ground. The output signal is representative of the magnitude and
direction of the rotation of the pendulous float about the output axis. The error signal is
then routed to the preamplifier mounted on the stable member. The phase of the output
signal from the preamplifier is -45° from the reference excitation. The phase shifted
zero or pi phase signals from the preamplifier are applied as separate inputs to the ac
differential amplifier and further amplified. The two signals are then sent to the
interrogator.
2-15
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MANUAL
The ac differential amplifier and the interrogator are packaged in the same module
which is located in the pulse torque assembly (PTA) (figure 2-10). The interrogator
analyzes the ac differential amplifier outputs to determine the direction of the 16
PIP float movement and generates appropriate torquing commands. The two ampli¬
fied signals from the ac differential amplifier goto two summing networks and threshold
amplifiers (represented in figure 2-10 by AND gates). Interrogate pulses (IP) are
continuously being received by the interrogator from the LGC. An interrogate pulse
is a two microsecond pulse occurring at 3,200 pps and timed to occur 135 degrees
after the positive going zero crossing of the reference excitation. (See figure 2-11.)
With this phasing, the interrogate pulse occurs at the 90 degree peaks of the phase shifted
zero or pi phase input signals from the PIP preamplifiers. The interrogate pulse
occurs at a positive 90 degree peak of the zero phase signal if the float angle is posi¬
tive and at a positive 90 degree peak of the pi phase signal if the float angle is negative.
The zero and pi phase signals and the interrogate pulses are ANDed by the summing
network and threshold amplifier. The gated outputs of the threshold amplifier are
applied to a flip-flop as set or reset pulses. If the flip-flop is in the +set condition,
a succession of set pulses will maintain the +set condition. The +set condition will
remain until the float angle passes through null. At this time, a reset pulse is pro¬
duced to cause the flip-flop to go to the -set condition.
SWITCH I 1
Figure 2-10. AC Differential Amplifier and Interrogator Module
2-16
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ND-1021042
MANUAL
The outputs of the flip-flop are applied to two AND gates which are also driven
by switch pulses received from the LGC. The switch pulses are a train of clock
driven 3,200 pps pulses three microseconds in width, timed to occur three micro¬
seconds after the leading edge of the interrogate pulse. The flip-flop enables only
one output gate at any switch pulse time. The outputs of the AND gates are called
the TM + set pulse and the TM - set pulse.
The binary current switch (figure 2-7) utilizes the TM + set and TM - set outputs of
the interrogator to generate 16 PIP torquing current. The TM + set and the TM - set
pulses furnish the input to a flip-flop. If the flip-flop is in the +set condition, a
succession of TM+set pulses will maintain the +set condition. The +set condition will
persist until the float angle passes through null. The phase change will cause the
flip-flop of the ac differential amplifier and interrogator module to reset to the -set
condition. At this time a TM - set pulse is developed and causes the binary current
switch flip-flop to go to the -set condition. The outputs of the flip-flop control two
transistor current switches. If the flip-flop is in the +set condition, the +set output will
be at the base of the +torque current switch and will turn it on. The +torque current
switch closes the path from the current regulated 120 vdc supply through the PIPA
calibration module to the 16 PIP T+ torque generator coils. If the flip-flop is in the
-set condition, the -torque current switch will be turned on, closing the path through
the T- torque generator coils.
An acceleration along the PIP input axis causes the pendulous mass to produce
a torque which tends to rotate the float about the output axis. The torque produced by
the acceleration is proportional to the magnitude of the acceleration. The acceleration
produced torque aids and opposes the torque generator forces causing changes in the
time required for the float to be torqued back through null. A change in velocity
(AV) is the product of acceleration and incremental time (At), the torque is actually
proportional to an incremental change in velocity ( AV).
tACCEL “ KlaAt - Kq AV
The float is already in motion due to loop torquing, therefore additional torque is
required to overcome the acceleration torque and to keep the pendulum in its oscilla¬
tory motion. The additional torque is obtained by supplying torquing current for addi¬
tional time through one of the torque windings. The current at any one time is a con¬
stant, therefore the current must be present for a longer period of time. Thus to
determine the amount of acceleration sensed by the PIP, it is necessary only to measure
the length of time torquing current is applied to each torque winding.
ACCELind = K2 E [(T+) - (T-)] At
2-17
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTIOl SYSTEM
ND-1021042
MANUAL
From the above identities, it is seen that torquing time (At) is proportional to the
change in velocity (AV).
Ki AV = K 2 £ [(T+) - (T-)] At
K2
AV - - £
The time ( At), representative of the AV, is sent to the LGC in the form of P and N
pulses (figure 2-9).
In addition to selecting the proper torque generator winding, the outputs of the
binary current switch flip-flop also go to two AND gates where they are ANDed with
the 3,200 cps data pulses from the LGC. The data pulse is three microseconds in
width and is timed to occur two microseconds after the leading edge of the switch pulse.
(See figure 2-11.) The data pulse and switch pulse are both 3,200 cps, therefore the
LGC receives either a P pulse or an N pulse once every 1 -f- 3200 second. When the
PIP is sensing no acceleration, the pendulum is oscillating at a frequency of 533-1/3
cps; and the LGC is receiving three P pulses and three N pulses once every cycle or
once every 1 -h 533-1/3 seconds. The LGC contains a forward-backward counter
which receives the velocity pulses and detects any actual gain in velocity.
The counter counts forward on the three P pulses and then backward on the three
N pulses. The counter continues this operation and generates no AV pulses. With
an acceleration input to the PIP, however, the loop no longer operates at the 3-3 ratio
and the counter exceeds its capacity and reads out the plus or minus AV pulses
which are then stored and used by the LGC. The additional pulses above the 3-3 ratio
are representative of the additional torque supplied by the torque generator to compen¬
sate for the acceleration felt by the LEM. Each pulse indicates a known value of Av
due to the loop scale factor.
The PIPA calibration module (figure 2-12) compensates for the inductive load
of the 16 PIP torque generator ducosyns and regulates the balance of the plus and minus
torques. The calibration module consists of two load compensation networks for the
torque generator coils of the 16 PIP. The load compensation networks tune the torque
generator coils to make them appear as a pure resistive load to the binary current
switch. A variable balance potentiometer regulates the amount of torque developed by
the torque generator coils. Adjustment of this potentiometer precisely regulates and
balances the amount of torque developed by the T+ and T- torque generator coils.
This balancing insures that for a given torquing current an equal amount of torque will
be developed in either direction.
2-18
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MANUAL
2-19
Figure 2-11. Accelerometer Timing
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Figure 2-12. PIP A Calibration Module
The calibration module also includes a current monitor resistor and an adjustable
scale factor resistor network in series with the torque generator coils. A nominal six
volts is developed across the scale factor resistor network due to the torquing current
and is applied as an input to the dc differential amplifier and precision voltage reference
module. The voltage drop across the current monitor resistor is used for external
monitoring purposes.
2-20
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MANUAL
The dc differential amplifier and PVR are identical to the ones used in the fine
align electronics. (See figure 2-8.) The dc differential amplifier and PVR module
maintain the current through the ducosyn torque generator coils at 43 milliamperes.
The PVR is supplied with regulated 28 vdc and, through the use of precision circuits,
develops an accurate 6 volts for use as a reference voltage. The scale factor resistor
in the calibration module also develops 6 volts when 43 milliamperes of current flows
through it. A comparison is made by the dc differential amplifier of the PVR 6 volts
and the scale factor 6 volts. Any deviation of the binary current switch torquing cur¬
rent from the nominal 43 milliamperes will increase or decrease the scale factor re¬
sistor voltage and result in an output error signal from the dc differential amplifier.
This error signal controls the current regulator in the binary current switch. The
current regulator, which is in series with the 120 vdc source and the ducosyn torque
generator coils, will maintain the torque current at 43 milliamperes.
2-4.4 IMU TEMPERATURE CONTROL SYSTEM
The IMU temperature control system (figure 2-13) maintains the temperature of
the stabilization gyros and accelerometers within the required temperature limits
during both standby and operating modes of the IMU. The system supplies and removes
heat to maintain the IMU heat balance with minimum power consumption. Heat is re¬
moved by convection, conduction, and radiation. The natural convection used during
IMU standby mode changes to blower controlled, forced convection during IMU opera¬
ting modes. The IMU internal pressure is maintained between 3.5 and 15 psia to enable
the required forced convection. To aid in removing heat, a water-glycol solution at
approximately 45.0 degrees Fahrenheit from the spacecraft coolant system passes
through the coolant passages in the IMU support gimbal.
2-4. 4.1 Temperature Control Circuit. The temperature control circuit maintains the
gyro and accelerometer temperature. The temperature control circuit consists of a
temperature control thermostat and heater assembly, a temperature control module,
three IRIG end mount heaters, three IRIG tapered mount heaters, two stable member
heaters, and three accelerometer heaters. The thermostat and heater assembly is
located on the stable member and contains a mercury-thallium thermostat, a bias
heater, and an anticipatory heater. Except for the bias heater, all heaters (a total of
12) are connected in parallel and are energized by 28 vdc through the switching
action of transistor Q2, which completes the dc return path. The thermostat acts as a
control sensing element and senses the temperature of the stable member.
2-21
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ND-1021042
MANUAL
When the temperature falls below 130 (±0.2) degrees Fahrenheit, the thermostat
opens and transistor Q1 conducts and drives transistor Q2 to conduction. When tran¬
sistor Q2 conducts, current will flow through the twelve heaters. Because of the large
mass of the stable member, its temperature will increase at a relatively slow rate as
compared to the gyros, which have a heater in each end mount. The anticipatory heater
improves the response of the thermostat to insure that the magnitude of the temperature
cycling of the gyros and the accelerometers is as small as possible. When the temper¬
ature rises above 130 (±0.2) degrees Fahrenheit, the thermostat closes and the base
of transistor Q1 is shorted to ground, cutting off transistors Q1 andQ2 and deenergizing
the heaters. The thermostat has a 0.5 degree deadband which is the difference between
contact closing with rising temperature and contact opening with falling temperature.
The temperature control circuit will maintain the average of the gyro temperatures at
135 (±1. 0) degrees Fahrenheit and the average of the accelerometer temperatures at
130 (±1. 0) degrees Fahrenheit under normal ambient conditions. The temperature
difference between the gyros and the accelerometers is adjusted by properly propor¬
tioning the amount of power in each heater. The balance is obtained by selection of
resistor Rl.
During IMU operation, power is applied to the fixed accelerometer heaters to
compensate for the additional heat supplied to the gyros by the gyro wheel motor
heat dissipation. Power is also applied to a bias heater on the control thermostat.
The bias heater supplies a fixed amount of heat to the control thermostat to maintain
the proper absolute temperature level of the gyros and accelerometers. The amount
of bias heat is controlled by the selection of resistor R5. The power for the fixed
accelerometer heaters and the thermostat bias heater are the -90 degree and -180
degree outputs, respectively, from the 28 vac power supplies which are also used
for gyro wheel power.
The 28 vdc heater power is applied to the heaters through the contacts of a safety
thermostat which will provide protection against an extreme overheat condition in
case a malfunction occurs in the temperature control circuit. The safety thermostat
contacts open at 139.5 (±3.0) degrees Fahrenheit and close at 137 (±3) degrees
Fahrenheit.
2-4. 4. 2 Blower Control Circuit. The blowers maintain IMU heat balance by removing
heat. The blowers operate continuously during IMU operate modes. The blower control
circuit shown on figure 2-13 is inoperative because the contacts of blower control
relay K1 are bypassed.
The blowers are supplied from the -90 and -180 degree outputs of the 28 volt,
800 cps, 2.5 percent power supply which also provides gyro wheel motor power. Fused
phase shift networks are associated with each blower so that excitation and control
current can be supplied from the same source.
2-22
1 TEMP ALARM
I THERMOSTAT
ASSY
ND-1021042
LEM PRIMARY GUIDANCE, NAVIGATION,
AND CONTROL SYSTEM
MANUAL
i 1 1
1 MIDDLE . OUTER i
GIM8AL | GIMBAL
CASE
LGC
i ! 1
I 1 GSNACE
PSA |
IMU AUXILIARY
MODULE
Figure 2-13. IMU Temperature Control System
2-23/2-24
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-4. 4. 3 Temperature Alarm Circuit. The temperature alarm circuit monitors the tem¬
perature control system. The temperature alarm circuit consists of a temperature
alarm thermostat and a temperature control module. If a high or low temperature is
sensed by the temperature alarm thermostat located on the stable member a discrete
is sent to the LGC and the IMU auxiliary module. When the temperature is within the
normal range of 126.3 to 134.3 degrees Fahrenheit, 28 vdc is applied through the ther¬
mostat to the emitter of transistor Q1 causing the transistor to conduct. Transistor
Q1 conducts through a grounding system in the LGC.
When the temperature falls below 126.3 degrees Fahrenheit, 28 vdc will be re¬
moved from transistor Ql, causing it to stop conducting and thus signaling the LGC
of an alarm condition. When the temperature rises above 134.3 degrees Fahrenheit,
28 vdc will be applied directly to the base of the transistor as well as to the emitter.
With 28 volts applied to both emitter and base, the base-emitter junction is no longer
forward biased and the transistor stops conducting which signals the LGC of an alarm
condition. There is no differentiation between a high or low temperature alarm. When
the LGC senses a temperature alarm, it causes the IMU TEMP lamp and the PGNCS
lamp to light. When the IMU auxiliary module receives a temperature alarm, it sends
the information to telemetry.
2-4. 4. 4 External Temperature Control. External temperature control of the IMU is
provided by GSE control heater circuits in the IMU which are controlled externally to
the airborne equipment by the portable temperature controller or the temperature
monitor control panel of the optics-inertial analyzer (OIA). The GSE control heater
circuitry consists of a safety thermostat, six gyro heaters, two stable member heaters,
three accelerometer heaters, temperature indicating sensors, and an IMU standby
power sensor which disables the GSE when airborne power is on. The temperature
indicating sensors act as the control sensing element of the external control and indi¬
cating circuitry. The heaters are connected in parallel. The six gyro temperature
indicating sensors (two in each gyro) are connected in series to sense the average
temperature of the gyros. The three accelerometer temperature indicating sensors
(one in each accelerometer) are connected in series to sense the average temperature
of the accelerometers. All of the GSE control heater circuitry is electrically indepen¬
dent of the airborne temperature control system and will not be used at the same time
that the IMU temperature is being controlled by the airborne temperature control sys¬
tem. The GSE control heater circuitry cannot be used as a backup temperature control
system during flight.
2-4.5 ISS MODES OF OPERATION. The ISS has four major modes of operation: IMU
turn on, CDU zero, coarse align, and inertial reference. Submodes which will also be
discussed are fine align, IMU cage, attitude error indication and display inertial data.
An additional mode is the master reset condition which is available during laboratory
testing only. All ISS moding is initiated and controlled by computer discretes to the
CDU. (See figure 2-14.) To select an ISS mode of operation, the LGC can send a single
discrete, a combination of discretes, or no discretes. The display inertial data func¬
tion utilizes the LORS channels of the CDU, therefore, a description of the discretes
to the LORS channels of the CDU will also be presented.
2-25
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-4. 5.1 CPU Discretes. All LGC discretes issued to the CDU to initiate and control
the various ISS modes or functions are 0. 0 (±2) vdc. LGC ground, applied through a
2, 000 ohm source impedance to the CDU mode module.
2-4. 5. 1.1 ISS CDU Zero. The ISS CDUzero discrete zeros or clears all three ISS CDU
read counters simultaneously. It also inhibits the transmission of incrementing pulses
to the read counters for the period of time the discrete is present. The CDU discrete
will be present (minimum duration is approximately 400 milliseconds) for as long as
the read counters are to be held at zero. The IMU is not disturbed by the CDU zero
discrete.
2-4. 5. 1.2 ISS Enable Error Counter. The ISS enable error counter discrete enables
all three ISS error counters simultaneously which allows them to accept incrementing
pulses from the LGC. The error counters are normally cleared and inhibited. The ISS
enable error counter discrete is used in conjunction with the coarse align enable discrete
during the coarse align mode. The ISS enable error counter enable discrete is used alone
when display of attitude error signals on the FDAI is required only.
2-4. 5. 1.3 Coarse Align Enable. The coarse align enable discrete enables a relay
driver which energizes the coarse align and demodulator reference relays located in
the PSA . This connects the coarse align error signal to the gimbal servo ampli¬
fiers and changes the reference voltage for the demodulator in the gimbal servo ampli¬
fiers from 3,200 cps to 800 cps. The discrete also enables the digital feedback pulses
from the read counter to the error counter. The presence of the coarse align enable
discrete and the absence of the enable error counter discrete also inhibit the increment¬
ing pulses to the read counter.
2-4. 5.1. 4 D /A Enable. The D/A enable discrete enables both LORSCDU error counters
simultaneously. The error counters are normally cleared and inhibited. The LGC nor¬
mally provides positioning signals to the optical tracker through the LORS channels
of the CDU. The D/A enable discrete, however, is also used in conjunction with the
display inertial data discrete to allow the LGC to feed inertially derived velocity data
through the LORS channels of the CDU to meter displays.
2-4. 5. 1.5 Display Inertial Data. The display inertial data discrete energizes relays
which switch the dc output from the digital to analog (D/A) converter in the LORS
channels of the CDU to the LEM velocity meters.
2-4. 5. 1.6 LORS CDU Zero. The LORS CDU zero discrete clears both LORS read
counters simultaneously and inhibits the transmission of incrementing pulses to the
read counters. This discrete is not used for any ISS flight modes or functions but can
be used for CDU test functions.
2-26
PSA
•3,200 CPS
IMU
0C SIGNAL
(NOT USED FOR LEM)
AC SIGNAL
TO FOAI
I
LEM PRIMARY GUIDANCE, NAVIGATION,
AND CONTROL SYSTEM
ND-1021042
MANUAL
rLGC
CDU
D/A CONVERTER
(800 CPS WOOER
NETWORK ANO (JEMODULATOR )
t tl t t t t
ERROR C<
UNTER
IL25*
5.6*
2 0*
1.4*
1
\
.17*
0.8*
044*
8
2
7
2
6
2
5
2
i
L3
2
2
2
0
2
+ A0C
+A0G
COARSE AND FINE ERROR SIGNALS
11
A/D SVf
CH
SELECTION
[OGIC
(COARsJ
Rnd
FINE SY!I
pMS)
ERROR
DETECTOR
t t t t t t t 1 1 1 t t t t t r
READ COUN-j
[r (*)
180*
90*
45*
225*
11.25*
5.6*
2.8*
•
1.4
•
.35°
.17*
08*
044*
022*
40*
ro
O
15
2
14
2
13
2
12
2
II
2
10
2
9
2
8
2
2'j
.7
6
2
5
2
4
2
3
2
2
2
2
0
2
A0G
•A0G
- AflG
EACH PULSE=022*X 2=0445(60 SEC'
+ A8G
5
MODE
LOGIC
28 VDC ISS OPERATE - WV-
MODE
LOGIC
RATE SELECT AND
UP-DOWN
LOGIC
6
4 KPPS
8
00 CPS
+ PI
EACH PULSE=20 SEC X 2=40 SEC
PHASE PULSES
FOR TIMING
MOOE
LOGIC
1
COARSE ALIGN
ENABLE (CA)
ISS ENABLE ERROR
COUNTER (EEC)
+ Aflc] ^
I 160 SEC/PULSE
> 3200 PPS
MAX RATE
— A0CJ
CLOCK 51.2 KPPS
( 6,400 PPS
MAX RATE )
CDU-ZERO (Z)
J L _
Figure 2-14. ISS-CDU Moding
2-27/2-28
t
4
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-4. 5. 2 IMU Turn On Mode. The purpose of the IMU turn on mode is to drive the
gimbals to their zero position and hold them there. (See figure 2-15.) The IMU turn
on mode is initiated upon closure of the ISS OPERATE circuit breaker and allows for
a 90 second gyro run up period. The ISS OPERATE circuit breaker routes 28 vdc IMU
operate power through the deenergized contacts of the ISS turn on control relay, located
in the IMU auxiliary assembly module, to the cage relays. The 28 vdc IMU operate
power is also routed through the same deenergized contacts to the LGC as a continuous
turn on delay request discrete. The cage relays energize and, in turn, cause the coarse
align relays to be energized. The cage relays route the IX gimbal resolver sine winding
outputs through the contacts of the coarse align relays to the respective gimbal servo
amplifiers. The gimbal servo amplifiers drive the gimbals until the resolver signals
are nulled. The operation of the caging loops is discussed further in the IMU cage
mode description.
Upon receipt of the ISS turn on delay request discrete, the LGC sends the ISS CDU
zero discrete and the coarse align enable discrete to the CDU for a minimum period of
90 seconds. The CDU zero discrete clears the read counters and inhibits the incrementing
pulses to the read counters. The coarse align enable discrete provides a redundant
means of energizing the coarse align relays.
A second set of deenergized contacts on the ISS turn on control relay routes a ground
to the time delay circuit of the pulse torque power supply which inhibits the operation
of the power supply and thus prevents accelerometer pulse torquing during the 90 second
turn on period. This allows time for the accelerometer floats to become centered
and the gyro wheels to run up prior to torquing.
After the 90 second delay has been completed, the LGC sends the ISS turn on delay
complete discrete. The ISS turn on delay complete discrete acts through a relay driver
to energize and latch in the ISS turn on control relay. Energizing the ISS turn on control
relay deenergizes the cage relay, removes the ISS turn on delay request discrete,
and removes the inhibit from the pulse torque power supply. The computer program
can then place the ISS in the inertial reference mode by removing both the CDU zero
and the coarse align enable discretes, or it can initiate the coarse align mode by re¬
moving only the CDU zero discrete and sending the ISS enable error counter discrete.
The IMU turn on circuit will be reset whenever 28 vdc IMU operate power is turned off.
2-4. 5. 3 IMU Cage Mode. The IMU cage mode is an emergency backup mode which
allows the astronaut to recover a tumbling IMU by setting the gimbals to zero. (See
figure 2-15.) During this mode, the IX gimbal resolver sine winding outputs are fed
through the CDU to the gimbal servo amplifiers to drive the gimbals until the resolver
signals are nulled.
2-29
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The IMU cage mode is initiated when the astronaut presses the IMU CAGE switch.
The switch is held until the gimbals settle at the zero position (five seconds maximum).
The gimbal position may be observed on the FDAI. The IMU CAGE switch routes a
28 vdc discrete signal to the LGC and to the cage relays located in the PSA. (See
figure 2-15.) The cage discrete energizes the cage relays, which in turn, cause the
coarse align relays, the demodulator reference relay, and a relay in the gimbal servo
amplifiers to energize. The relay in the gimbal servo amplifiers switches in addi¬
tional capacitance into the RC compensation networks to tune them for 800 cps operation.
The demodulator reference relay changes the gimbal servo amplifier demodulator refer¬
ence signal from 3,200 cps to 800 cps. The cage relays switch the IX gimbal resolver
sine winding outputs through the energized contacts of the coarse align relays into the
corresponding gimbal servo amplifier inputs. The gimbal servo amplifiers drive the
gimbals until the resolver signals are nulled.
Upon receipt of the IMU cage discrete, the LGC will discontinue sending the error
counter enable discrete, the coarse align enable, the display inertial data discrete, and
the incrementing pulses to the CDU. The LGC will also discontinue sending torquing
commands, if any are in process, to the fine align electronics.
After the IMU CAGE switch is released, the LGC will allow the read counters to
settle and will then place the PGNCS in an attitude control mode. During the time the
IMU cage discrete is present and while the read counters are settling, the NO ATT lamp
on the DSKY is lighted.
The cage mode will also be entered automatically if the IMU is turned on when the
LGC is off or in standby mode. During the normal turn on sequence, the closure of the
ISS OPERATE circuit breaker will route 28 vdc through the deenergized contacts of
the ISS turn on control relay to the cage relays. The cage relays energize and cage the
gimbals. After the 90 second turn on time delay has been completed, the LGC will
send the ISS turn on delay complete discrete which will energize the ISS turn on control
relay which, in turn, deenergizes the cage relays. If, however, the LGC is off or in
standby when the IMU is turned on, the ISS turn on control relay will remain deenergized
and the ISS will remain in the IMU cage mode.
If the IMU cage mode is entered as a result of an IMU turn on with the LGC off
or in standby, the ISS can be placed in the inertial reference mode by allowing 90
seconds for gyro runup then pressing the IMU CAGE switch. The IMU CAGE switch
will energize and latch in the ISS turn on control relay which removes the 28 vdc which
had been energizing the cage relays. With the ISS turn on control relay latched, the
cage relays will deenergize and remain deenergized when the IMU CAGE switch is
released. Deenergizing the cage relays causes the coarse align relays to be deenergized
which connects the gyro error signals to the respective gimbal servo amplifiers.
The stabilization loops will maintain the stable member inertially referenced to the
orientation established by the caging loops.
2-30
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
1
2-31/2-32
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-4. 5. 4 ISS CPU Zero. The purpose of the ISS CDU zero mode is to clear and inhibit
the three ISS CDU read counters. (See figure 2-14.) The mode is initiated by the LGC
sending the ISS CDU zero discrete. The presence of the discrete is maintained for as
long as the read counters are to be held at zero.
2-4. 5.5 Coarse Align Mode. The purpose of the coarse align mode is to change the
orientation of the gimbals by LGC command. The change in gimbal orientation is accom¬
plished by feeding the CDU error counter computer pulses equal to the required change
in gimbal angles. The mode is initiated when the LGC sends the coarse align discrete
and, after a short delay, the ISS error counter enable discrete to the three ISS portions
of the CDU. When the mode is entered, the CDU read counter will be in the process of
repeating the gimbal angle and supplying angular data to the LGC and will continue to
do so for the duration of the coarse align mode. The LGC, knowing the actual gimbal
angle registered in the read counter, calculates the desired amount of change in gimbal
angle required to reposition the gimbal to the desired angle and converts this change
into a number of ±A 9C pulses to be sent to the error counter. The ±A 6C pulses are sent
to the error counter at a rate of 3, 200 pps in bursts of 80 milliseconds duration. Bursts
of pulses are sent 600 milliseconds apart. EachA0c pulse is equal to a change in gimbal
angle of 160 arc seconds. The error counter, having been enabled, accepts the pulses
and counts up or down, as necessary, until all the pulses have been registered.
The digital information in the error counter is converted into an 800 cps, amplitude
modulated, analog error signal by the ladder decoder in the D/A converter module. The
ladder decoder signal is summed with a feedback signal and applied through a mixing
amplifier located in the D/A converter module to the gimbal servo amplifiers to drive
the gimbals to the desired angles. The function of the feedback signal and the mixing
amplifier will be discussed later. The output of the mixing amplifier, referred to as
the coarse align error signal, is applied to the gimbal servo amplifiers through the con¬
tacts of the coarse align relays located in the PSA. The coarse align relays, which
are energized by the coarse align enable discrete acting through a relay driver, switch
the input of gimbal servo amplifiers from the gyro preamplifiers to the coarse align
error signal output of the ISS D/A converter. The demodulator reference relay is also
energized by the coarse align enable discrete and switches the reference frequency of
the demodulator in the gimbal servo amplifiers from 3,200 cps to 800 cps. The coarse
align enable discrete also energizes a relay in the gimbal servo amplifiers which switches
in additional capacitance into the amplifier’s compensation networks to tune them for
800 cps operation.
As the gimbals are driven, ±A0cpulses, representing the change in actual gimbal
angle, are generated by the read counter and applied to the error counter. TheA06 pulses
are also equal to 160 arc seconds and act to decrease theA0c pulses registered in the
error counter. The error counter output to the ladder decoder, therefore, represents
the difference between the desired amount of change in gimbal angle and the amount
of change actually accomplished. When the error counter reaches a null and the gimbals
stop moving, the actual gimbal angle has changed by an amount equal to the total value
of the ±A0C pulses sent by the LGC to the error counter.
2-33
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The rate at which the gimbals are driven is limited to prevent damage to the gyros
and to assure that the read counter can track the gimbal angle accurately. The rate of
gimbal movement is limited by feeding back the C DU fine error signal [sin 16 (0-0)] to
the input of the mixing amplifier located in the D/A converter module. The CDU fine
error signal is out of phase with the output of the ladder decoder and has an amplitude
proportional to the difference between the actual gimbal angle (0) and the angle in the
read counter (0). The fine error signal is applied through a voltage limiting cir¬
cuit to the summing junction of the mixing amplifier where it is summed with the 800
cps ladder decoder output signal. The D/A converter ladder decoder output is applied
to the mixing amplifier through a scaling amplifier and a voltage limiting diode net¬
work. The scaling amplifier controls the signal gain to produce a scale factor of 0.3
volt rms per degree. The output of the mixing amplifier will be at a null when the D/A
converter ladder decoder output, after limiting, is equal to the fine error feedback
signal. The fine error signal will be a constant value only when the gimbal and the
CDU are going at the same rate and with the gimbal angle leading the CDU angle.
Since the CDU is limited to counting at one of two speeds, the gimbals will be limited
to a rate equal to one of these two speeds. During the coarse align mode, the CDU
is limited to a high counting speed of 6.4 kpps and a low counting speed of 800 cps.
At all othertimes, the high counting speed is 12.8 kpps.
If the gimbals are moving at a faster rate than the rate at which the CDU is counting,
the fine error signal will increase, causing a retarding torque to be developed by the
gimbal servo amplifier. If the gimbals are moving at a rate slower than the rate at
which the CDU is counting, the fine error signal will decrease, causing the gimbal
servo amplifier to apply an accelerating torque to the gimbals. By adjusting the gain of
the fine error signal into the mixing amplifier, the gimbal drive rate is limited to
either 35. 5 degrees per second (6.4 kpps CDU counting rate) or 4.5 degrees per second
(800 cps CDU counting rate).
2-4. 5.6 Inertial Reference Mode. The inertial reference mode provides a coordinate
reference system on which attitude and velocity measurements and calculations may be
based. During the inertial reference mode, the stable member is held fixed with respect
to an inertial reference by the stabilization loops. The ISS CDU read counters provide
the LGC with changes in gimbal angles with respect to the stable member. The ISS is
in the inertial reference mode during any operating period in which there is an absence
of moding commands. During the inertial reference mode, the fine align electronics is
inhibited and the ISS CDU error counters are cleared and inhibited.
2-4.5.7 Fine Align Mode. The purpose of the fine align mode is to reposition the stable
member to a fine alignment by torquing the gyros. The fine align mode is actually a
gyro torquing function accomplished during the inertial reference mode. The torquing
current to the gyros is provided by the fine align electronics located in the PTA. The
fine align electronics is enabled and controlled by LGC pulses sent directly to the fine
align electronics. The LGC does not send command discretes to the ISS CDU’s during
this mode. The ISS is in the inertial reference mode prior to the enabling of the fine
align electronics and returns to that mode when the fine align electronics is disabled.
2-34
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The fine align electronics torques the gyros on a time shared basis. The LGC sends
four types of pulse trains to the fine align electronics. The first pulse train sent
is the torque enable command which enables the fine align electronics. The second
pulse train is a gyro select command which selects a particular gyro and the direction
it is to be torqued by means of a switching network which closes the current path
through the proper torque ducosyn coil. The third and fourth types of pulse trains
are the torque set and torque reset commands which control a binary current switch
to start and stop the current flow through the selected torque ducosyn coil. The amount
of current flow through the torque ducosyn coils is precisely controlled at a fixed value.
The amount of gyro torquing to accomplished is determined by the amount of time.torque
current is applied, that is, the time duration between the receipt of the torque set and
the torque reset commands. This time duration is calculated by the LGC programs and
may be based on optical alignment measurements. The torque ducosyn displaces the
gyro float, causing the ducosyn signal generator to apply an error signal to the sta¬
bilization loop. The stabilization loops drive the gimbals to reposition the stable mem¬
ber. Upon completion of the torquing, the stable member remains fixed in its inertial
reference and in fine align mode until the torque enable command is removed, after
which the ISS remains in inertial reference mode until further change is commanded.
During the fine align mode, the ISS error counters remain cleared and inhibited.
The read counters continue to repeat the gimbal angles and send angular data (±A0G) to
the LGC.
2-4. 5. 8 Attitude Error Indication. The attitude error indication mode supplies attitude
error signals to the FDAI. The attitude error indication mode is initiated when the
LGC sends the ISS error counter enable discrete to the CDU. The LGC will calculate
the difference between the actual gimbal angles and the correct angles and convert
this into the number of ±A©C pulses to be sent to the error counter. The error counter,
having been enabled, accepts the pulses and counts up or down until it has registered
all the pulses.
As the actual gimbal angles increase or decrease, ±Aqg pulses, which represent
the change in actual gimbal angle, are generated by the read counter and applied to the
error counter. The ±A0G pulses cause the error counter to count up or down and, in
effect, register the difference between the actual gimbal angle and the desired gimbal
angle. The digital information in the error counter is converted into an 800 cps, ampli¬
tude modulated, analog error signal by the ladder decoder in the D/A converter.
This ac signal is applied through a scaling amplifier to the FDAI.
2-4. 5. 9 Display Inertial Data. The display inertial data mode permits the LGC to pro¬
vide inertially derived forward and lateral velocity signals through the digital to analog
section of the LORS channels of the CDU to the LEM velocity display meters. The
display inertial data mode is used during the last phases of the LEM powered descent.
2-35
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The display inertial data mode is requested by the astronaut closing a switch on the
main control panel. (See figure 2-16.) The mode is initiated by the LGC sending the
display inertial data discrete to the LORS channels of the CDU. The display inertial
data discrete acts through a relay driver to energize relays which connect the D/A
converter dc error signal outputs to the LEM velocity display meters. After a brief
delay to allow for relay pull in time, the LGC sends the D/A enable discrete followed
by incrementing pulses to the error counters. The LGC sends ±Aec pulses representing
LEM forward velocity (motion along the Zlem axis) to one error counter and ±A0c
pulses representing LEM lateral velocity (motion along the vehicle Ylem) to
other error counter. The read counters will not send incrementing pulses to the error
counters; therefore, the only information registered in the error counters will be
the ±Aoc pulses.
The digital information registered in the error counter is converted into an 800
cps, amplitude modulated, analog signal by the ladder decoder in the D/A converter.
This signal is converted into a positive dc analog signal by a phase sensitive demodulator
circuit also located in the D/A converter. The dc analog signal is applied through the
energized relay contacts to the LEM velocity display meters. As the velocity changes,
as calculated by the LGC, representative ± A0c pulses will continue to be sent to the
error counter, causing it to count up or down and thereby changing the D/A converter
dc signal to the display meters.
L_
0/A CONVERTER
(800 CPS LADDER
NETWORK AND DEMODULATOR)
t t t t t t t t t
ERROR COUNTER
w.zi
5 6*
2.8*
14*
.7*
.35*
.17*
0.8*
44*
28
2?
2 6
2 5
24
2 3
22
2 1
2 0
MOOE
LOGIC
D6PLAY INERTIAL
DATA REQUEST
D/A ENABLE
+ A0C
~ A 0 cj
I
160 SEC
| _ LGC _
15637
Figure 2-16. Display Inertial Data Mode
2-36
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-4.5.10 Master Reset Condition (Test Area Only). The purpose of the master reset
condition is to establish preselected standard operating modes in both the airborne
equipment and the GSE. The master reset condition is operable in the ISS test con¬
figuration only. The master reset condition is initiated when the MASTER RESET
pushbutton on the test control panel of the OIA is pressed.
The effects of establishing a master reset condition are dependent upon the particular
ISS level of test, power mode status, et cetera, at the time the MASTER RESET push¬
button is pressed. With the ISS STANDBY pushbutton selected, but prior to pressing the
ISS OPERATE pushbutton, the MASTER RESET pushbutton will cause the simultaneous
closure of the IMU stabilization loops. During the first 90 seconds after pressing
the ISS OPERATE pushbutton, the MASTER RESET pushbutton is disabled. Ninety
seconds after pressing the ISS OPERATE pushbutton, the MASTER RESET push¬
button is enabled and, if selected, simultaneously performs the following operations:
causes the coarse align mode to be commanded, places the gimbals under gimbal
positioner control, and removes all IMU caging signals. The master reset condition
also discontinues all LORS mode commands and commands the LORS channels of the
CDU to repeat the LORS angles.
2-4.6 ISS POWER SUPPLIES.
The ISS power supplies convert the +28 vdc prime LEM power into the various
dc and ac voltages required by the ISS. The power supplies are the pulse torque
power supply; the -28 vdc power supply; the 800 cps, 1 percent power supply; the 800
cps, 5 percent, 2 phase, power supply; and the 3,200 cps power supply. The pulse
torque power supply is in the PTA and the remaining power supplies are in the PSA.
The +28 vdc prime power is supplied by the LEM electrical power system through
the ISS OPERATE circuit breaker. All ac power supplies are synchronized to the LGC
clock by means of computer pulses. Thedc supplies, using multivibrators as ac sources
for transformation, are also synchronized to the LGC. Synchronization is accomplished
by a multivibrator which will free runata lower frequency without the computer pulses,
assuring operation of the ISS power supplies in the event of an LGC failure.
2-4. 6.1 Pulse Torque Power Supply. The pulse torque power supply (figure 2-17)
provides 120 vdc to the three binary current switches and three dc differential ampli¬
fiers in the accelerometer loops and the binary current switch and dc differential
amplifier in the stabilization loop fine align electronics. The pulse torque power supply
also provides three individual 28 vdc outputs to the accelerometer loop PVR’s, 20 vdc
to the three accelerometer loop ac differential amplifier and interrogator modules
and the associated binary current switches, and -20 vdc to the ac differential ampli¬
fier and interrogator module in the accelerometer loops.
The -20 vdc output is derived from the -28 vdc power supply by using a zener
diode as a voltage divider and regulator. The output is regulated at -20(±0.8) vdc.
The 20 vdc output is derived from 28 vdc prime power by the use of a three tran¬
sistor series regulator which maintains the output voltage at 20 (±0.55) vdc.
2-37
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
I523I-B
Figure 2-17. Pulse Torque Power Supply
The 120 vdc and 28 vdc PVR outputs are derived from a multivibrator, a power
amplifier, and a rectifier and filter. A 12.8 kpps synchronizing pulse is received from
the LGC through a buffer transformer in the pulse torque insolation transformer assem¬
bly and is applied to an amplifier-inverter. The output of the amplifier-inverter is
applied to a multivibrator-chopper causing it to be synchronized at 6,400 cps. A tran¬
sistorized time delay circuit is incorporated into the emitter circuits of the multi¬
vibrator to provide a turn on time delay of approximately 350 milliseconds. During the
90 second IMU turn on mode, 0 vdc is applied through the turn on circuits of the IMU
auxiliary assembly module to the time delay circuit which inhibits the 120 vdc and
2-38
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
28 vdc PVR supplies. The multivibrator-chopper output is applied to the primary of
a transformer which has 28 vdc prime power applied to its center tap. The secondary
of the transformer, which is also center tapped, is coupled to a two stage push-pull
power amplifier which operates from 28 vdc prime power. The output of the power
amplifier consists of a transformer with four secondary windings; one with center tap
return for the 120 vdc power supply, and one each for the X, Y, and Z accelerometer
loop 28 vdc PVR supplies. The 120 vdc power supply consists of a full wave rectifier
whose output is filtered, regulated, and again filtered. The 28 vdc power supplies are
identical and consist of a full wave bridge rectifier whose output is filtered, regulated,
and again filtered. The PVR time delay circuit inhibits the operation of the regulator
in each 28 vdc PVR circuit to provide a six to eight second time delay in the 28 vdc PVR
outputs.
2-4. 6. 2 -28 VDC Power Supply. The -28 vdc power supply provides input power to the
three gimbal servo amplifiers in the stabilization loops and to the pulse torque power
supply to generate -20 vdc foruseinthe accelerometer loops. The -28 vdc power supply
consists of a pulse amplifier-inverter, a multivibrator-chopper, a power amplifier, and
a rectifier and filter. (See figure 2-18.) The 25.6 kpps synchronization pulse input is
amplified and inverted for use in synchronizing the multivibrator-chopper at 12.8 kcps.
The multivibrator-chopper output is applied to the primary of a transformer which has
28 vdc prime power applied to its center tap. The secondary of the transformer, which
is also center tapped, is coupled to a push-pull power amplifier. The output of the
amplifier is transformer coupled to a full wave rectifier and filter whose positive side
is referenced to ground to provide a -27.0 (±1.0) vdc output.
2-4. 6.3 800 CPS Power Supply. The 800 cps power supply (figure 2-19) consists of four
modules; an automatic amplitude control, filter, and multivibrator; a 1 percent ampli¬
fier; and two 5 percent amplifiers. The 1 percent amplifier provides IMU gimbal resolver
excitation, gimbal servo amplifier demodulator reference, and FDAI and autopilot
reference. The two 5 percent amplifiers provide gyro wheel excitation, IMU blower
excitation, and accelerometer fixed heater power. The 1 percent amplifier also provides
the input to one of the 5 percent amplifiers whose output is phase shifted -90 degrees.
The output of this 5 percent amplifier is applied to the second 5 percent amplifier
whose output is also phase shifted -90 degrees, or -180 degrees from the output of the
1 percent amplifier. The outputs of the 1 percent amplifier and the 5 percent ampli¬
fiers are applied to their respective loads through the IMU load compensation network
which provides a power factor correction.
Zero and pi phase, 800 cps pulse trains from the LGC synchronize the multivibrator
at 800 cps. In the absence of the synchronizing pulses, the multivibrator will free run
at between 720 and 800 cps. The output of the multivibrator controls the operation of the
chopper and filter circuit. The filtered chopper output is applied to the 1 percent ampli¬
fier. The output of the 1 percent amplifier, in addition to its direct uses, is a feedback
signal to the automatic amplitude control circuit. The positive peaks of this feedback
signal are detected and added to a dereference signal. The sum is filtered and provides
a dc bias to the multivibrator driven chopper. The bias controls the amplitude of the
chopped signal.
2-39
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
20 VDC
PRIME
POWER
FROM LGC
25 6KPPS
0 PHASE
PULSE
AMPL-
INVERTER
«
MULTI-
VIBRATOR
CHOPPER
FULL
WAVE
RECTIFIER
8 FILTER
— 27.5 VDC
I5230C
Figure 2-18. -28 VDC Power Supply
28vll.5%
800 CPS
0* PHASE
20 V + 5.0%
800 CPS
-90* PHASE
(A PHASE)
28V t 7.5%
800 CPS
- 180* PHASE
(8 PHASE)
152288
Figure 2-19. 800 CPS Power Supply
2-40
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The 1 percent amplifier is push-pull in operation with transformer coupled input
and output and with overall voltage feedback for gain and distortion control.
The two 5 percent amplifiers are identical in operation. The amplifiers are
push-pull and have transformer coupled inputs and outputs. The input transformer
primary center tap is connected to the input signal low. The input signal high is applied
directly to one side of the primary winding and is also applied through a phase shift
network to the other, or out of phase, side of the primary. A feedback signal from the
secondary of the output transformer is also applied to the out of phase side of the input
transformer primary where it is mixed with the phase shifted portion of the input signal.
This mixing results in a -90 degree phase shift in the secondary of the input transformer.
The output of the first 5 percent amplifier is used as an input to the second 5 percent
amplifier to provide an additional -90 degree phase shift.
2-4. 6. 4 3,200 CPS Power Supply. The 3,200 cps power supply provides excitation
voltage for the signal generator and the magnetic suspension portions of the IRIGand PIP
ducosyns. The 3, 200 cps output is also used as a reference for the demodulator in the
gimbal servo amplifiers.
The excitation voltage to the signal generators requires both voltage stability and
phase stability. To accomplish this stability, the excitation voltage power transmission
to the stable member is through a step down transformer on the stable member which
reduces the slip ring current and, therefore, voltage dropeffects due to slip ring, cable,
and connector resistance. In addition, each wire connecting the output of the transformer
to the input terminals of each PIP is cut to exactly the same length. The voltage level at
the primary of the transformer is fed back to the power supply and is compared to a
voltage reference.
The 3, 200 cps power supply (figure 2-20) consists of an amplitude control module
and a 1 percent power amplifier. The amplitude control module contains an automatic
amplitude control circuit, a multivibrator, a chopper, and a filter.
The 3, 200 pps pulse trains of zero degree phase and 180 degree phase synchronize
a multivibrator. The output of the multivibrator controls the operation of the chopper
circuit. The output of the chopper is applied to the 1 percent power amplifier. The
28 volt rms output of the amplifier is transmitted through the slip rings to the trans¬
former on the stable member where the voltage is stepped down to 2 volts for the accel¬
erometer ducosyns and 4 volts for the gyro ducosyns. A sample of the 28 volt level at
the primary of the transformer is fed back through the slip rings to the input of the
automatic amplitude control circuit. The positive peaks of the feedback signal are
detected and added to a dc reference signal. The sum is filtered and provides a dc bias
to the chopper circuit. The dc bias controls the amplitude of the chopper output to the
filter.
2-5 LEM OPTICAL RENDEZVOUS SUBSYSTEM
This paragraph will give a functional description of the LORS and it will link the
LORS operations to systems level operations. This paragraph will be supplied when
information is available.
2-41
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
I - 1
[ IMU ]
I5229C
Figure 2-20. 3,200 CPS Power Supply
2-6 COMPUTER SUBSYSTEM
The computer subsystem (CSS) is the control and processing center of the PGNCS.
It consists of the LGC and a DSKY. The CSS processes data and issues discrete outputs
and control pulses to the PGNCS and other LEM systems. The LGC is a parallel digital
control computer with many features of a general purpose computer. As a control
computer, the LGC aligns the IMU, positions the optical tracker, and issues control
commands to other LEM systems. As a general purpose computer, the LGC solves the
guidance and navigation equations required for the LEM mission. In addition, the LGC
monitors the operation of the LEM, including the CSS.
The main functions of the LGC (see figure 2-21) are implemented through the ex¬
ecution of the programs stored in memory. Programs are written in a machine language
called basic instructions. A basic instruction contains an operation (order) code and a
relevant address. The order code defines the data flow within the LGC, and the relevant
address selects the data that is to be used for computations. The order code of each
instruction is entered into the sequence generator, which controls data flow and pro¬
duces a different sequence of control pulses for each instruction. Each instruction is
followed by another instruction. In order to specify the sequence in which consecutive
instructions are to be executed, the instructions are normally stored in successive
memory locations. By adding the quantity one to the address of an instruction being
executed, the address of the instruction to be executed next is derived. Execution of an
instruction is complete when the order code of the next instruction is transferred to the
sequence generator and the relevant address is in the central processor.
2-42
- DATA FLOW
- CONTROL SIGNALS
4-28VDC
PRIMARY
INPUT
POWER
SUPPLY
4- 4 V, 14V
(TO all
FUNCTIONAL
AREASI
FROM
SPACECRAFT
MODE / STATUS SIGNALS
ENGINE SIGNALS
TELEMETRY
FROM
INERTIAL
SUBSYSTEM
GIMBAL ANGLES (CDU)
VELOCITY INCREMENTS
(PIPA)
FROM {
LEM OPTICAL TRACKER ANGLES(CDU) - -»
RENDEZVOUS <
SUBSYSTEM | MODE DISCRETES - »
STABILIZATION
AND CONTROL
SYSTEM
TRANSLATION, ROTATION ,
AND IMPULSE SIGNALS
INPUT
NTERFACE
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FROM PONCS
MODE AND
CAUTION SIGNALS
1 E YBOARD INPUTS
DISPLAY
AND
KEYBOARD
MODE AND
CAUTION SIGNALS
\ TO PGNCS
' AND
SPACECRAFT
DISPLAY DATA
AND CAUTION
SIGNALS
INPUT
CHANNELS
SEOUENCE
GENERATOR
INPUT
LOGIC
CENTRAL
PROCESSOR
OUTPUT
CHANNELS
REAL time
KEYRUPJ _AND
HNDRPT
INCREMENTAL
PULSES
PRIORITY
CONTROL
OUTPUT
INTERFACE
OUTPUT
SYNC SIGNALS
I
- TIMER
TIMING SIGNALS
(TO ALL AREAS)
MASTER CLOCK AND
ENGINE CONTROL SIGNALS
RADAR TIMING SIGNALS
DOWNLINK DATA
CDU DRIVE PULSES
PIPA INTERR 8 SWITCH
GYRO DRIVE PULSES
.CDU DRIVE PULSES
TIMING SIGNALS
TIMING SIGNALS
PITCH, YAW. ANO
ROLL SIGNALS
TO SPACECRAFT
TO INERTIAL
SUBSYSTEM
TO
LEM OPTICAL
RENDEZVOUS
SUBSYSTEM
TO PSA
TO
STABILIZATION
AND CONTROL
SYSTEM
Figure 2-21. Computer Subsystem,
Block Diagram
2-43/2-44
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The central processor consists of several flip-flop registers. It performs arithmetic
operations and data manipulations on information accepted from memory, the input
channels, and priority control. Arithmetic operations are performed using the ONE's
complement number system. Values of 14 bits, excluding sign, (up to 28 bits during
double precision operations) are processed with an additional bit produced for overflow
or underflow. All operations within the central processor are performed under control
of pulses generated by the sequence generator (indicated by dashed lines in figure 2-21).
In addition, all words read out of memory are checked for correct parity, and a parity
bit is generated within the central processor for all words written into memory. The
LGC uses odd parity, that is, all words stored in memory contain an odd number of
ONE's including the parity bit. The central processor also supplies data and control
signals through the output channel's and provides interface for the various spacecraft
subsystems.
The LGC has provision for nine program interrupts. These interrupts are: T6 RUPT,
T5 RUPT, T4 RUPT, T3 RUPT, KEYRUPT, UPRUPT, DOWNRUPT, RADAR, and
HNDRPT. The T6 RUPT through T4 RUPT programs are initiated by the LGC. The
DOWNRUPT program is initiated at the completion of every parallel-to-serial conversion
for downlink operation. The remaining interrupt programs are initiated by external
inputs to the LGC. The KEYRUPT programs are initiated when a DSKY pushbutton
is depressed or when priority control receives a signal (discrete bit) from the optical
tracker to indicate a sighting. The UPRUPT and RADAR programs are initiated when
a complete UPLINK word (used for unmanned flights) is received. The HNDRPT
program is initiated as soon as a hand controller is moved out of detent by the astronaut.
Before a priority program can be executed, the current program must be inter¬
rupted; however, certain information about the current program must be preserved.
This information includes the program counter contents and any intermediate results
contained in the central processor. The priority control produces an interrupt request
signal, which is sent to the sequence generator. This signal, acting as an order code,
causes the execution of an instruction that transfers the current contents of the program
counter and any intermediate results to memory. In addition, the control pulses transfer
the priority program address in priority control to the central processor, and then to
memory through the write lines. As a result, the first basic instruction word of the
priority program is entered into the central processor from memory, and execution of
the priority program is begun. The last instruction of each priority program restores
the LGC to normal operation, provided no other interrupt request is present, by trans¬
ferring the previous program counter and intermediate results from their storage loca¬
tions in memory back to the central processor.
Certain data pertaining to the flight of the LEM is used to solve the guidance
and navigation problems required for the LEM mission. This data, which includes
real time, acceleration, and IMU gimbal angles, is stored in memory locations called
counters. The counters are updated as soon as new data becomes available. An
incrementing process which changes the contents of the counters is implemented by
2-45
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
priority control between the execution of basic instructions. Data inputs to priority
control are called incremental pulses. Each incremental pulse produces a counter
address and a priority request. The priority request signal is sent to the sequence
generator, where it functions as an order code. The control pulses produced by the
sequence generator transfer the counter address to memory through the write lines of
the central processor. In addition, the control pulses enter into the central processor
the contents of the addressed counter to be incremented.
Real time plays a major role in solving guidance and navigation problems. Real
time is maintained within the LGC in the main time counter of memory. The main time
counter provides a 745. 65 hour (approximately 31 days) clock. Incremental pulses are
produced in the timer and sent to priority control for incrementing the main time counter.
The LEM mission requires that the LGC clock be synchronized with the KSC
clock. The LGC time is transmitted once every second by downlink operation for
comparison with the KSC clock.
Incremental transmissions occur in the form of pulse bursts from the output
channels to the CDU, the gyro fine align electronics, the RCS of the spacecraft, the
optical tracker and the radar. The number of pulses and the time at which they occur
are controlled by the LGC program. Discrete outputs also originate in the output
channels under program control. These outputs are sent to the DSKY and various
other subsystems. Continuous pulse trains originate in the timing output logic for
synchronization of other systems.
The uplink word from the LEM telemetry system (unmanned flights) is supplied as
an incremental pulse input to priority control. As this word is received, priority control
procudes the address of the uplinkcounter in memory and requests the sequence gener¬
ator to execute the instructions which perform the serial-to-parallel conversion of the
input word. When the serial-to-parallel conversion is completed, the parallel word is
transferred to a storage location in memory by the uplink priority program. The uplink
program also retains the parallel word for subsequent downlink transmission. Another
program converts the parallel word to a coded display format and transfers the display
information to the DSKY.
The downlink operation of the LGC is asynchronous with respect to the LEM telemetry
system. The telemetry system supplies all the timing signals necessary for the downlink
operation. These signals include start, end, and bit sync pulses.
Through the DSKY, the astronaut can load information into the LGC, retrieve and
display information contained in the LGC, and initiate any program stored in memory.
A keycode is assigned to each keyboard pushbutton. When a keyboard pushbutton on the
DSKY is depressed, the keycode is produced and sent to an input channel. A signal is
also sent to priority control, where it produces both the address of a priority program
stored in memory and apriority request signal, which is sent to the sequence generator.
This operation results in an order code and initiates an instruction for interrupting the
program in progress and executing the KEYRUPT priority program stored in memory.
2-46
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
A function of this program is to transfer the keycode, temporarily stored in an input
channel, to the central processor, where it is decoded and processed. A number of
keycodes are required to specify an address, or a data word. The program initiated by
a keycode also converts the information from the DSKY keyboard to a coded display
format. The coded display format is transferred by another program to an output channel
and sent to the display portion of the DSKY. The display notifies the astronaut that the
keycode was received, decoded, and processed properly by the LGC.
2-6.1 PROGRAMS. An LGC program performs such functions as solving guidance and
navigation problems, testing the operation of the PGNCS, and monitoring the operation
of the LEM. Such a program consists of a group of program sections that are classified
according to the functions they perform. These functions are defined as mission
functions, auxiliary functions, and utility functions. (See figure 2-22.)
2-6. 1. 1 Mission Functions. Mission functions are performed by program sections that
implement operations concerned with the major objectives of the LEM mission. These
operations include erecting the IMU stable member and coarse aligning it to a desired
heading prior to separating the LEM from the CSM and fine aligning it after separation.
In addition, the mission functions include computation of spacecraft position and velocity
during coasting periods of the flight by solution of second-order differential equations
which describe the motions of a body subject to the forces of gravity.
2-6. 1.2 Auxiliary Functions. Auxiliary functions are executed at the occurrence of
certain events, requests, or commands. These functions are performed by program
sections that provide a link between the LGC and other elements of the PGNCS. This
link enables the LGC to process signals from various devices and to send commands for
control and display purposes. In addition, the auxiliary functions implement many and
varied operations within the LGC in support of the LEM mission functions.
ITnput/output
L
1 [memory
I I
J L
1
J
40383
Figure 2-22. Program Organization
2-47
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-6. 1.3 Utility Functions. Utility functions are performed by program sections that
coordinate and synchronize LGC activities to guarantee orderly and timely execution
of required operations. These functions control the operation of the LEM mission functions
and schedule LGC operations on either a priority or a real-time basis. The utility
functions also translate interpretive language to basic machine language which allows
complex mathematical operations such as matrix multiplication, vector addition, and
dot product computations to be performed within the framework of compact routines.
In addition, the utility functions save the contents of registers A and Q during an inter¬
rupt condition and enable data retrieval and control transfer between isolated banks
in the fixed- switchable portion of fixed memory.
2-6.2 MACHINE INSTRUCTIONS. The LGC has three classes of machine instructions:
regular, involuntary, and peripheral (table 2-1). Regular instructions are programmed
and are executed in whatever sequence they have been stored in memory. Involuntary
instructions (with one exception) are not programmable and have priority over regular
instructions. One involuntary instruction may be programmed to test computer opera¬
tions. No regular instruction can be executed when the LGC forces the execution of an
involuntary instruction. The peripheral instructions are used when the LGC is connected
to the peripheral equipment. During the execution of any peripheral instruction, the
LGC is in the monitor stop mode and cannot perform any program operation.
2-6.2. 1 Regular Instructions. Four types of instructions comprise the regular instruc¬
tion class. They are the basic, channel, extracode, and special instructions. Basic
instructions are used most frequently. The instruction words stored in memory
are called basic instruction words. They contain an order code field and an
address field. Special instructions have predefined addresses and order codes; basic
instructions have only predefined order codes. The special instructions are used to
control certain operations in the LGC. For example, one special instruction is used
to switch the LGC to the extend mode of operation. This mode extends the length of the
order code field and converts basic instruction words to channel or extracode instruction
words. Channel instructions can only be used with input-output channel addresses. Extra
code instructions perform the more complex and less frequently used arithmetic oper¬
ations.
Regular instructions can also be functionally subdivided into the following:
(1) Sequence changing.
(2) Fetching and storing.
(3) Modifying.
(4) Arithmetic and logic.
(5) Input- output.
(6) Editing.
2-48
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 2-1. Instruction Classes
Class
Type
Control
Regular
Basic
Extracode
Channel
Special
Program
Involuntary
Interrupt
Counter
Priority
Peripheral
Keyboard
Tape
Operator
The sequence changing instructions alter the sequence in which the instructions
stored in memory are executed. One group, called transfer control instructions, changes
the program path as defined by the programmer. The other group, called decision
making instructions, branches to alternate program paths in response to predefined
conditions.
The fetching and storing instructions move data, without alteration, from one loca¬
tion to another. One group, called copy instructions, provides a non-destructive transfer
of data from memory to the central processor. Another group, called exchange in¬
structions, transposes data between memory and the central processor. One instruc¬
tion provides a nondestructive transfer of data from the central processor to memory.
The modifying instructions alter the next instruction to be executed by changing the
contents of the order code field, address field, or both.
The arithmetic and logic instructions perform numerical computations. One group,
called the basic arithmetic instructions, performs addition, subtraction, multiplication,
and division in the ONE'S complement number system. Another group, called the add
and store instructions, performs single or double precision addition and transfers the
resultant from the central processor to memory. The incrementing instructions incre¬
ment a signed quantity, increment its absolute value, or diminish its absolute value by
one. One instruction performs subtraction in the TWO's complement number system
for angular data and one instruction performs the Boolean AND operation.
The input-output or channel instructions link the interface circuits to the central
processor. One group, called read instructions, transfers the total or partial contents
of any channel (register) location to the central processor either directly or accompanied
by the Boolean AND, OR, or EXCLUSIVE OR operation. Another group of instructions
transfers all new or partially new information to any channel location in the same manner.
2-49
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The editing or special instructions are address-dependent and control the operation
of the program. One special instruction, as mentioned previously, controls the extend
mode of operation. Other instructions prevent a program from being interrupted or
shift and cycle data to the left or right.
2-6. 2. 2 Involuntary Instructions. Involuntary instructions contain two types of instruc¬
tions: interrupt and counter. The interrupt instructions use the basic instruction word
format just as the regular instructions do; however, the interrupt instructions are not
entirely programmable. The contents of the order code field and the address field are
supplied by computer logic rather than the program. The counter instructions have no
instruction word format. Signals which function as a decoded order code specify the
counter instruction to be executed and the computer logic supplies the address. The
address for these instructions is limited to one of 29 counter locations in memory.
There are two interrupt instructions. One instruction initializes the LGC when
power is first applied and when certain program traps occur. The other interrupt in¬
struction is executed at regular intervals to indicate time, receipt of new telemetry or
keyboard data, or transmission of data by the LGC. This interrupt instruction may be
programmed to test the computer.
There are several counter instructions. Two instructions will either increment or
decrement by one the content of the counter location using the ONE'S complement number
system. Two other instructions perform the same function using the TWO's complement
number system. Certain counter instructions control output rate signals and convert
serial telemetry data to parallel computer data.
2-6. 2. 3 Peripheral Instructions. There are two types of peripheral instructions. One
type deals' with memory locations and the other type deals with channel locations. The
peripheral instructions are not used when the LGC is in the LEM. They are used when
the computer is connected to peripheral equipment during subsystem and preinstallation
system testing. The peripheral instructions are not programmable and are executed
when all computer program operations have been forcibly stopped. These instructions
are used to read and load any memory or channel location and to start the computer
program at any specified address. The peripheral instructions and counter instructions
are processed identically.
2-6.3 TIMER. The timer generates the timing signals required for operation of the
LGC and is the primary source of timing signals for all LEM systems.
The timer is divided into the areas indicated in figure 2-23. The master clock fre¬
quency is generated by an oscillator and is applied to the clock divider logic. The divider
logic divides the master clock input into gating and timing pulses at the basic clock rate
of the computer. Several outputs are available from the scaler, which further divides
the divider logic output into output pulses and signals which are used for gating, for
generating rate signal outputs, and for accumulating time. Outputs from the divider
logic also drive the time pulse generator which produces a recurring setof time pulses.
This setof time pulses defines a specific interval (memory cycle time) in which access
to memory and word flow take place within the computer.
2-50
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
GATING AND
TIMING PULSES
PULSE AND
SIGNAL OUTPUTS
TIME PULSES
STOP
40686*
Figure 2-23. Timer, Block Diagram
The start- stop logic senses the status of the power supplies and specific alarm
conditions in the computer and generates a stop signal which is applied to the time pulse
generator to inhibit word flow. Simultaneous with the generation of the stop signal, a
fresh start signal is generated which is applied to all functional areas in the computer.
The start- stop logic and subsequent word flow in the computer can also be controlled
by inputs from the Computer Test Set (CTS) during pre-installation systems and sub¬
system tests.
2-6.4 SEQUENCE GENERATOR. The sequence generator executes the instructions
stored in memory. The sequence generator processes instruction codes and produces
control pulses which regulate the data flow of the computer. The control pulses are
responsible for performing the operations assigned to each instruction in conjunction
with the various registers in the central processor and the data stored in memory.
The sequence generator (figure 2-24) consists of the order code processor, com¬
mand generator, and control pulse generator. The sequence generator receives order
code signals from the central processor and priority control. These signals are coded
by the order code processor and supplied to the command generator. The special purpose
control pulses are used for gating the order code signals into the sequence generator at
the end of each instruction.
The command generator receives instruction signals from priority control and
peripheral equipment and receives coded signals from the order code processor. The
command generator decodes the input signals and produces instruction commands which
are supplied to the control pulse generator.
2-51
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
Figure 2-24. Sequence Generator, Block Diagram
The control pulse generator receives twelve time pulses from the timer. These
pulses occur in cycles and are used for producing control pulses in conjunction with
the instruction commands. There are five types of control pulses: read, write, test,
direct exchange, and special purpose. Information in the central processor is trans¬
ferred from one register to another by the read, write, and direct exchange control
pulses. The special purpose control pulses regulate the operation of the order code
processor. The test control pulses are used within the control pulse generator. The
branch test data from the central processor changes the control pulse sequence of
various instructions.
2-6.5 CENTRAL PROCESSOR. The central processor, figure 2-25, consists of the
flip-flop registers, the write, clear, and read control logic, write amplifiers, memory
buffer register, memory address register, and decoder and the parity logic. All data
and arithmetic manipulations within the LGC take place in the central processor.
Primarily, the central processor performs operations indicated by the basic in¬
structions of the program stored in memory. Communication within the central pro¬
cessor is accomplished through the write amplifiers. Data flows from memory to the
flip-flop registers or vice-versa, between individual flip-flop registers, or into the
central processor from external sources. In all instances, data is placed on the write
lines and routed to a specific register or to another functional area under control of
the write, clear, and read logic. This logic section accepts control pulses from the
sequence generator and generates signals to read the content of a register onto the
write lines and to write this content into another register of the central processor or
to another functional area of the LGC. The particular memory location is specified by
the content of the memory address register. The address is fed from the write lines
into this register, the output of which is decoded by the address decoder logic. Data is
subsequently transferred from memory to the memory buffer register. The decoded
address outputs are also used as gating functions within the LGC.
2-52
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Figure 2-25. Central Processor, Block Diagram
The memory buffer register buffers all information read out or written into memory.
During readout, parity is checked by the parity logic and an alarm is generated in case
of incorrect parity. During write-in, the parity logic generates a parity bit for informa¬
tion being written into memory. The flip-flop registers perform the data manipulations
and arithmetic operations. Each register is 16 bits or one computer word in length.
Data flows into and out of each register as dictated by control pulses associated with
each register. The control pulses are generated by the write, clear, and read control
logic.
External inputs through the write amplifiers include the content of both the erasable
and fixed memory bank registers, all interrupt addresses from priority control, control
pulses which are associated with specific arithmetic operations, and the start address
for an initial start condition. Information from the input and output channels is placed
on the write lines and routed to specific destinations either within or external to the
central processor. The CTS inputs allow a word to be placed on the write lines during
system and subsystem tests.
•
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
2-6.6 PRIORITY CONTROL. Priority control is related to the sequence generator in
that it controls all involuntary or priority instructions. The priority control processes
input-output information and issues order code and instruction signals to the sequence
generator and issues twelve-bit addresses to the central processor.
The priority control (figure 2-26) consists of the start, interrupt, and counter in¬
struction control circuits. The start instruction control initializes the computer if the
program works itself into a trap, if a transient power failure occurs, or if the interrupt
instruction control is not functioning properly. The computer is initialized with the
start order code signal, which not only forces the sequence generator to execute the
start instruction, but also resets many other computer circuits. When the start order
code signal is being issued, the T12 stop signal is sent to the timer. This signal stops
the time pulse generator until all essential circuits have been reset and the start in¬
struction has been forced by the sequence generator. The computer may also be initial¬
ized manually when connected to the peripheral equipment and placed into the monitor
stop mode. In this mode, the time pulse generator is held at the T12 position until the
monitor stop signal is released.
SEQUENCE
GENERATOR
CENTRAL
'PROCESSOR
SEQUENCE
GENERATOR
SPACECRAFT
4 0689
Figure 2-26. Priority Control, Block Diagram
#
2-54
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The interrupt instruction control can force the execution of the interrupt instruction
by sending the interrupt order code signal to the sequence generator and the twelve bit
address to the central processor. There are ten addresses, each of which accounts for
a particular function that is regulated by the interrupt instruction control. The interrupt
instruction control links the keyboard, telemetry, and time counters to program oper¬
ations. The interrupt addresses are transferred to the central processor by read control
pulses from the sequence generator. The source of the keyboard, telemetry, and time
counter inputs is the input-output circuits. The interrupt instruction control has a built-
in priority chain which allows sequential control of the ten interrupt addresses. The
decoded interrupt addresses from the central processor are used to control the priority
operation.
The counter instruction control is similar to the interrupt instruction control in that
it links input-output functions to the program. It also supplies twelve-bit addresses to
the central processor and instruction signals to the sequence generator. The instruction
signals cause a delay (not an interruption) in the program by forcing the sequence gen¬
erator to execute a counter instruction. The addresses are transferred to the central
processor by read control pulses. The counter instruction control also has a built-in
priority of the 29 addresses it can supply to the central processor. This priority is also
controlled by decoded counter address signals from the central processor. The counter
instruction control contains an alarm detector which produces an alarm if an incremental
pulse is not processed properly.
2-6.7 INPUT-OUTPUT. The input-output section accepts all inputs to, and routes to
other systems all outputs from, the computer. The input-output section (figure 2-27)
includes the interface circuits, input and output channels, input logic, output timing logic,
and the downlink circuits.
START SYNC AND
TO OUTPUT
INTERFACE
DOWNLINK WORD
KEYCOOE TO DSKY
STABILIZATION AND
CONTROL SYSTEM
OUTPUTS
PGNCS OUTPUTS
RADAR ACTIVITY
OUTPUTS
INERTIAL SUB¬
SYSTEM OUTPUTS
TIMING SIGNALS
TO PGNCS
AND SPACECRAFT
I5808B
Figure 2-27. Input-Output, Block Diagram
2-55
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Most of the input and output channels are flip-flop registers similar to the flip-flop
registers of the central processor. Certain discrete inputs are applied to individual
gating circuits which are part of the input channel structure, typical inputs to the chan¬
nels include keycodes from the DSKY and signals from the PGNCS proper and other
LEM systems. Input data is applied directly to the input channels; there is no write pro¬
cess as in the central processor. However, the data is read out to the central processor
under program control. The input logic circuits accept inputs which cause interrupt
sequences within the computer. These incremental inputs (acceleration data from the
PIPA’s, et cetera) are applied to the priority control circuits and subsequently to asso¬
ciated counters in erasable memory.
Outputs from the computer are placed in the output channels and are routed to specific
systems through the output interface circuits. The operation is identical to that in the
central processor. Data is written into an output channel from the write lines and read¬
out to the interface circuits under program control. Typically, these outputs include
outputs to the stabilization and control system, the DSKY, the PGNCS, et cetera. The
downlink word is also loaded into an output channel and routed to the LEM spacecraft
telemetry system by the downlink circuits.
The output timing logic gates synchronization pulses (fixed outputs) to the PGNCS
and the LEM spacecraft. These are continuous outputs since the logic is specifically
powered during normal operation of the computer and during standby.
2-6.8 MEMORY. Memory (figure 2-28) consists of an erasable memory with a storage
capacity of 2048 words and a fixed core rope memory with a storage capacity of 36, 864
words. Erasable memory is a random-access, destructive-readout storage device. Data
stored in erasable memory can be altered or updated. Fixed memory is a nondestructive
storage device. Data stored in fixed memory is unalterable since the data is wired in
and readout is nondestructive.
Both memories contain magnetic-core storage elements. In erasable memory, the
storage elements form a core array; infixed memory, the storage elements form three
core ropes. Erasable memory has a density of one word per 16 cores: fixed memory
has a density of eight words per core. Each word is located by an address.
In fixed memory, addresses are assigned to instruction words to specify the sequence
in which they are to be executed; blocks of addresses are reserved for data, such as
constants and tables. Information is placed into fixed memory permanently by weaving
patterns through the magnetic cores. The information is written into assigned locations
in erasable memory with the CTS, the DSKY, uplink, or program operation.
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CENTRAL
PROCESSOR*
REGISTER G
(CENTRAL PROCESSOR)
40691
Figure 2-28. Memory, Block Diagram
Both memories use a common address register (register S)and an address decoder
in the central processor. When resister S contains an address pertaining to erasable
memory, the erasable memory cycle timing is energized. Timing pulses sent to the
erasable memory cycle timing then produce strobe signals for the read, write, and sense
functions. The erasable memory selection logic receives an address and a decoded
address from the central processor and produces selection signals which permits data
to be written into or read out of a selected storage location. When a word is read out of
a storage location in erasable memory, the location is cleared. A word is written into
erasable memory through the memory buffer register (register G) in the central pro¬
cessor by a write strobe operation. A word read from a storage location is applied to
the sense amplifiers. The sense amplifiers are strobed and the information is entered
into register G of the central processor. Register G receives information from both
memories.
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The address in register S energizes the fixed memory cycle timing when a location
in fixed memory is addressed. The timing pulses sent to the fixed memory cycle timing
produce the strobe signals for the read and sense functions. The selection logic receives
an address from the write lines, a decoded address and addresses from register S, and
produces selection signals for the core rope. The content of a storage location in fixed
memory is strobed from the fixed memory sense amplifiers to the erasable memory
sense amplifiers and then entered into register G of the central processor.
2-6.9 POWER SUPPLIES. The two power supplies (figure 2-29) furnish operating volt¬
ages to the LGC and the DSKY. Primary power of 28 vdc from the spacecraft is
applied to both power supplies. Regulator circuits maintain a constant output of +4 volts
and +4 volts switched from one supply, and +14 volts and +14 volts switched from the
other. The regulator circuits are driven by a sync signal input from the timer, each
power supply having a different sync frequency. During system and subsystem tests,
inputs from the CTS can be used to simulate power supply failures.
The standby mode of operation is initiated by pressing the standby (STBY) pushbutton
on the DSKY. During standby, the LGC is put into a RESTART condition and the switch-
able +4 and +14 voltages are switched off, thus putting the LGC into a low power mode
where only the timer and a few auxiliary signals are operative.
VOLTAGE
ALARM
FRESH
START
+ 4VDC
(SWITCHED)
+I4VDC
(SWITCHED)
OSCILLATOR
■M4VDC -
+ 4VDC
(SWITCHED)
+14 VDC
(SWITCHED)
SCALER
+ 4VDC
+I4VDC
OSCILLATOR
ALARM
SCALER
ALARM
FRESH
START
SCALER
FAIL
FILTER IN
+ 4VDC
( SWITCHEO )
+ I4VDC
(SWITCHED)
WARNING
INTEGRATOR
FILTER
OUT
Figure 2-29.
Power Supplies, Block Diagram
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The voltage alarm circuits monitor the +28, +14, and +4 volt outputs and produce
an LGC restart signal (Fresh Start) should any of the voltages deviate from nominal by
more than a predetermined amount. The oscillator alarm produces an LGC restart
signal (Fresh Start) if the oscillator fails or if the LGC is in the standby mode. The
scaler alarm circuit monitors the scaler output of the timer and generates a fail signal
if the scaler output fails. The warning integrator monitors certain operations and gen¬
erates an LGC warning signal (Filter Out) if these operations are frequently repeated
or prolonged.
2-6. 10 DISPLAY AND KEYBOARD. The DSKY is located below the center panels of the
cockpit display and control panels.
The DSKY (figure 2-30) consists of a keyboard; a relay matrix with associated de¬
coding circuits, displays, mode and caution circuits; and a power supply. The keyboard,
which contains several numerical, sign, and other control keys, allows the astronaut to
communicate with the LGC. The inputs from the keyboard are entered into an input
channel and processed by the LGC.
COMPUTER
OUTPUT
CHANNEL 10
KEYCOOE INPUTS TO COMPUTER
CAUTION SIGNALS TO PGNCS
MODE AND CAUTION SIGNALS
TO PGNCS ANO SPACECRAFT
15106
Figure 2-30. Display and Keyboard (DSKY), Block Diagram
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The inputs entered from the keyboard, as well as other information, appear on the
displays after processing by program. The display of information is accomplished through
the relay matrix. A unique code for the characters to be displayed is formed by fifteen
bits from output channel 10 in the LGC. Bits 12 through 15 are decoded by the decoding
circuits, and, along with bits 1 through 11, energize specific relays in the matrix which
causes the appropriate characters to illuminate . The information displayed is the result
of a keycode punched in by the astronaut, or is computer-controlled information. The
display characters are formed by electroluminescent segments which are energized by
a voltage from the power supply routed through relay contacts. Specific inputs from the
PGNCS are also applied, through the LGC to certain relays in the matrix through output
channel 10 of the LGC. The resulting relay- controlled outputs are caution signals to the
PGNCS.
The mode and caution circuits accept direct input signals from channels 11, 12, and
13, without being decoded. The resulting outputs can give an indication to the astronaut
on the DSKY and route the output signal to the PGNCS and spacecraft.
2-60
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Chapter 3
PHYSICAL DESCRIPTION
3-1 SCOPE
This chapter describes the physical characteristics of the components which com¬
prise the LEM PGNCS. The PGNCS components and their locations within the LEM
are listed in table 3-1 and illustrated in figure 3-1. The locations of PGNCS component
modules are also illustrated and the module functions described.
3-2 PGNCS INTERCONNECT HARNESS
The PGNCS interconnect harness (composed of harnesses A and B) interconnects
the components of the PGNCS and provides the electrical interface between the PGNCS
and other LEM systems. The IMU and PTA are interconnected by harness B. Harness
A interconnects the PSA, CDU, LGC, and signal conditioner. The two harnesses are
connected to each other by vehicle cables. Table 3-II lists the harness connectors
and the components or cable to which they are mated.
Table 3-1. LEM PGNCS Components
Component
Part Number
Location
CDU
2007222-041
Mounted on coldplate on center
section of after crew compart¬
ment wall.
PGNCS interconnect
harness
6014515-011
Harness A
6014506
Attached to rear wall of after
crew compartment
Harness B
6014507
Located in IMU compartment.
(Sheet 1 of 2)
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Table 3-1. LEM PGNCS Components
Component
Part Number
Location
IMU and PTA
6007001-011
IMU
2018601-011
Bolted to after end of nav base.
PTA
6007000-011
Mounted on coldplate on^LEM
structure immediately aft of
IMU/nav base complex.
LEM guidance
computer group
6003001-021
DSKY
2003985-031
Mounted to front wall of crew
compartment below LEM display
and control panel.
LGC
2003100-021
Mounted on coldplate on upper
section of after crew compart¬
ment wall above CDU.
Luminous beacon
Mounted on coldplate on CSM
on upper bulkhead of service
module.
Nav base
6899950-011
Bolted to LEM structure in
unpressurized compartment
above astronauts1 heads.
Optical tracker
Bolted to forward end of nav
base and extending outside
LEM.
PSA
6007200-011
Mounted on coldplate on lower
section of after crew compart¬
ment wall below CDU.
Signal conditioner
Attached to top of PSA.
(Sheet 2 of 2)
3-2
PTA
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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3-3
Figure 3-1. Location of LEM PGNCS Components
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
Table 3-II. PGNCS Harness Interconnections
PGNCS Harness
Connector
Component
Component
Connector
Harness A
56P1
Signal conditioner
-
56P2
PSA
45J19
56P3
CDU
40J53
56P4
LGC
05A1J51
56P5
LEM spacecraft harness
J221
56P6
LEM spacecraft harness
J220
56P7
LEM spacecraft harness
J219
56P8
LEM spacecraft harness
J222
56P9
LEM spacecraft harness
J218
56P10
LEM spacecraft harness
J217
56P11
LEM spacecraft harness
J223
56P12
LEM spacecraft harness
J224
56P13
LEM spacecraft harness
J215
56P14
LEM spacecraft harness
J216
Harness B
56P15
LEM spacecraft harness
J226
56P16
LEM spacecraft harness
J227
56P17
LEM spacecraft harness
J228
56P18
LEM spacecraft harness
J225
56P19
PTA
35A2J19
56P20
IMU
35A1J2
56P21
IMU
35A1J1
56J1
LEM spacecraft harness
P230
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3-3 NAVIGATION BASE ASSEMBLY
The navigation base assembly (nav base), figure 3-2, is a lightweight mount
which supports, in critical alignment, the IMU and optical tracker. The nav base,
constructed of one inch diameter, aluminum alloy tubing, weighs approximately three
pounds. It consists of a center ring supporting four legs which extend from either side.
The ring is approximately 14 inches in diameter and each of the four legs is approxi¬
mately ten inches long. The IMU is mounted to the ends of the four legs on one side
of the ring, and the optical tracker is mounted to the opposite ends of the legs. The
nav base is bolted to the LEM structure above the astronauts’ heads by three mounting
pads on the center ring.
3-4 INERTIAL MEASURING UNIT
The IMU (figure 3-3) is a three gimbal system designed for movement of the LEM
about all axes of the gyro-stabilized inner gimbal (stable member). To provide light¬
weight, rigid construction, the stable member is machined from a beryllium block
and the gimbals are constructed of an aluminum alloy. The weight of the IMU is
approximately 42 pounds, and the gimbal case is approximately 12.5 inches in diameter.
I tt4l
Figure 3-2. Navigation Base Assembly
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Three Apollo II IRIG's hold the stable member in a stabilized condition. Accelera¬
tions along any component of any of the three orthogonal axes of the stable member are
sensed by one or more of the three 16 PIP accelerometers. Intergimbal assemblies
physically support the gimbals and pass electrical signals between them. The tem¬
perature of the IMU is maintained at the desired level by a system of heaters, blowers,
and coolant passages. The IMU is pressurized to aid in convection cooling.
3-4.1 STABLE MEMBER. The stable member, or inner gimbal, is suspended by two
intergimbal assemblies inside the middle gimbal. It is free to rotate without restriction
about the inner gimbal (IG) axis. Holes are machined in the beryllium block to receive
the three Apollo II IRIG’s and three 16 PIP’s. Accelerometer preamplifiers, stable
member heaters, temperature control circuitry and thermostats, a ducosyn trans¬
former, and two safety thermostats are all attached to the stable member.
Figure 3-3. Inertial Measuring Unit
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3-4. 1. 1 Gyroscopes. The three gyroscopes (gyros) on the stable member are Apollo n
ERIG types. Figure 3-4 shows the location of the gyros on the stable member.
Ducosyns are used for magnetic suspension of the gyro rotor and for signal and
torque generation. The signal generator ducosyn is located at one end of the float; the
torque generator ducosyn is located at the other end.
The gyro wheel assembly operates as a hysteresis synchronous motor. The hub of
the wheel is made of beryllium and the rim is made of heavy steel. This method of con¬
struction concentrates the weight at the rim, giving the wheel a high inertial moment.
3-4. 1.2 Accelerometers. The LEM IMU uses three 16 PIP devices for sensing acc¬
eleration. Figure 3-4 shows the orthogonal placement of the 16 PIP's on the stable
member. The 16 PIP is basically a cylindrical float with a pendulous mass unbalance
and is pivoted with respect to a case. Ducosyns are located at each end of the float for
magnetic suspension and signal and torque generation.
3-4. 1.3 Stable Member Mounted Electronics. Table 3-III gives the locations and functions
of electronics modules which are mounted in the IMU.
3-4.2 MIDDLE GIMBAL. The middle gimbal is suspended by two intergimbal assem¬
blies inside the outer gimbal. It, in turn, supports the stable member. Slip ring assem¬
blies in the intergimbal assemblies provide a means of carrying electrical signals
between the outer gimbal and the stable member.
3-4.3 OUTER GIMBAL. The outer gimbal is similar in configuration to the middle gim¬
bal, being suspended inside the supporting gimbal, or case, by two intergimbal assem¬
blies. The outer gimbal has two thermostatically controlled axial-flow blowers mounted
in its walls to force air from the vicinity of the middle gimbal to the walls of the case,
where heat is carried away by a coolant solution circulating through passages in the
case.
3-4.4 SUPPORTING GIMBAL. The supporting gimbal (case) is a spherical enclosure
which supports the three gimbals described in the preceding paragraphs. The outer
gimbal is suspended inside the case by two intergimbal assemblies which allow com¬
plete freedom of rotation. The walls of the case contain coolant passages through which
a water-glycol solutionis circulated to dissipate heat generated by inertial components
and electronic modules. Two quick-disconnect fittings connect the coolant passages to
the LEM coolant supply. The case is surrounded by insulating material to prevent con¬
densation of moisture on the coolant passages.
Electrical interface between the IMU and the remainder of the PGNCS is accom¬
plished by two electrical connectors on the case. A precision resolver alignment as¬
sembly module and a blower control relay are mounted on the resolver inter-gimbal
assembly of the outer gimbal. Their functions are described in table 3 -III. Theresolver
alignment assembly is accessible from outside the case.
3-7
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Figure 3-4. IMU Stable Member
3-8
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MANUAL
Table 3 -in. Locations and Functions of IMU Electronics
Module or Component
Part Number
Location and Function
Blower control module
assembly
2007171-011
Stable member (SM): Removes power
from blower control relay in response to
request from blower control thermostat.
Blower control thermo¬
stat and heater assem¬
bly
2018635
SM: Controls on-off action of blower
motors on outer gimbal.
Temperature control
module assembly
2007064-011
SM: Applies power to gyro, accelero¬
meter, and stable member heaters in
response to request from temperature
control thermostat.
Temperature control
thermostat and heater
assembly
2018637
SM: Controls operation of temperature
control module to maintain proper
heat in inertial components.
Stable member heater
assembly (2)
2018641
SM: Supplement heat generated by
inertial component heaters.
Safety thermostat (2)
1001485
SM: Disable all IMU heaters in the
event of an extreme overheat condition.
Temperature alarm
module assembly
2007170-011
SM: Signals LGC that an overheat
or underheat condition is present.
Temperature alarm
thermostat assembly
2018636
SM: Controls operation of temperature
alarm module assembly.
Ducosyn transformer
assembly
2007019-011
SM: Reduces 28 vac to 2 volts and
4 volts for signal generator excitation
of accelerometer and gyro ducosyns,
respectively.
PIP preamplifier
assembly (3)
2007060-011
SM: Amplifies signals generated by
accelerometer signal generator. Also
provides 45 degree phase shift from
reference voltage.
(Sheet 1 of 2)
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Table 3-III. Locations and Functions of IMU Electronics
Module or Component
Part Number
Location and Function
Precision resolver
alignment assembly
2007001-011
Outer gimbal resolver intergimbal
assembly: Compensates for design
anomalies in intergimbal assembly
resolvers.
Blower control relay
1010353-10
Outer gimbal resolver intergimbal
assembly: Applies power to blower
motors at request of blower control
module assembly.
(Sheet 2 of 2)
3-4.5 INTERGIMBAL ASSEMBLIES. The intergimbal assemblies serve five basic
purposes: the duplex ball bearings support the gimbal with a minimum of friction,
the torque motor drives the gimbal in response to an error signal, the multispeed
resolver furnishes signals which represent the angular disposition of the gimbal, the
slip rings allow passing of electrical signals from the stable member to the external
connectors, and the gyro error resolver (inner gimbal only) transforms gyro error
signals into gimbal angle error signals.
3-5 OPTICAL TRACKER
The optical tracker, figure 3-5, is the active portion of the LEM optical rendezvous
subsystem. The optical tracker and its detection and control circuitry is mounted on
the four forward legs of the nav base.
The optical tracker telescope is driven about two axes, elevation and azimuth.
The telescope assembly which houses the optics and rotates about the elevation axis
(Y), has a direct drive torque motor and tachometer on one side and IX and 16X re¬
solvers and a potentiometer on the other side. The outer gimbal, which houses the tele¬
scope assembly and rotates about the azimuth axis(X), has a direct drive torque motor,
IX and 16X resolvers, and a tachometer mounted along the azimuth axis.
The telescope assembly is free to rotate 360 degrees in either direction in azimuth
from the zero position, which is parallel to the -YLEM axis. Elevation travel is limited
to 20 degrees below the LEM +Z axis to 20 degrees above the -Z axis. A flange, bolted
to the base of the optical tracker, serves as a mechanical stop to prevent contact of the
telescope assembly with the skin of the LEM.
3-10
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Figure 3-5. Optical Tracker
3-11
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Figure 3-6. Luminous Beacon
3-6 LUMINOUS BEACON
The luminous beacon (figure 3-6) consists of two complete beacon systems and a
common controller housed in a single package. Each beacon system consists of a power
supply, a xenon flash tube, and the necessary optics to produce a radiant output beam.
The luminous beacon is located on the adapter ring between the command and service
module.
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3-7 PULSE TORQUE ASSEMBLY
The PTA, figure 3-7, consists of 17 electronic modular assemblies mounted on a
common base. The cover, which is fitted over the modules and attached to the light¬
weight magnesium base, has a filler valve that is used to pressurize the unit. The
assembled unit, measuring approximately 2.5 inches high, 11 inches wide, and 13 inches
deep and weighing approximately 15 pounds, is mounted to a coldplate in the LEM.
The PTA supplies inputs to and processes outputs from the inertial components
in the IMU. To avoid line loss in low-level signals, the PTA is mounted close to the
IMU. Table 3-IV identifies and lists the functions and locations of the PTA modules.
The base, or header, of the PTA has two connectors: J19 which mates with the
PGNCS interconnect harness and test connector J18 which breaks out specific signals
for monitoring purposes during testing. Table 3-V lists the signals, by pin number,
available at jack J18.
Figure 3-7. Pulse Torque Assembly
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Table 3-IV. Locations and Functions of PTA Modules
Module
Part Number
Function
Location
Binary
Current
switch (4)
2007103-011
One furnishes torquing
current to the three
Apollo n IRIG’s and
three furnish torquing
current to the indivi¬
dual 16 PIP’s.
DC differen¬
tial amplifier
and precision
voltage ref¬
erence (4)
2007101-011
Regulate torquing cur¬
rent supplied through
binary current
switches.
run n
X
Y
|z
0
BO
AC differen¬
tial amplifier
and interro¬
gator (3)
2007104-011
Amplify accelerometer
signal generator sig¬
nals and convert them
to plus and minus
torque pulses.
HQ
Gyro cali¬
bration
module
2007102-011
Applies plus or minus
torque pulses to
Apollo n IRIG’s when
directed by LGC.
(Sheet 1 of 2)
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Table 3-IV. Locations and Function of PTA Modules
Module
Part Number
Function
Location
Pulse tor¬
que power
supply
2007106-011
Supplies 120 vdc to dc
differential amplifier
and binary current
switch during gyro
torquing routines.
PIPA cali¬
bration
module (3)
6007105-011
Compensate for differ¬
ences in inductive
loading of accelerom¬
eter signal generator
windings and regulate
balance of plus and
minus torques.
Pulse torque
isolation
transformer
6007005-011
Couples torque com¬
mands, data pulses,
interrogate pulses,
switching pulses, and
synchronizing pulses
between LGC and PTA.
r— 3 0
0
(J
bq
(Sheet 2 of 2)
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Table 3-V. PTA Test Points
Pin
Number
Signal
Description
D2
Y PIPA current
monitor (low)
D3
Z PIPA current
monitor (low)
D4
IRIG current
monitor (low)
D5
0 vdc IMU X PIPA
error monitor
(low)
D6
0 vdc IMU Y PIPA
error monitor
(low)
D7
0 vdc IMU Z PIPA
error monitor
(low)
FI
X PIPA current
monitor (high)
F2
Y PIPA current
monitor (high)
F3
Z PIPA current
monitor (high)
F4
IRIG current
monitor (high)
G5
-20 vdc (high)
G6
0 vdc IMU
(±20 vdc) (low)
G7
+ 20 vdc (high)
Pin
Number
Signal
Description
A5
X PIPA P pulses
A6
Y PIPA P pulses
A7
Z PIPA P pulses
B1
X PIPA PVR (high)
B2
Y PIPA PVR (high)
B3
Z PIPA PVR (high)
B4
IRIG PVR (high)
B5
X PIPA N pulses
B6
Y PIPA N pulses
B7
Z PIPA N pulses
Cl
X PIPA PVR (low)
C2
Y PIPA PVR (low)
C3
Z PIPA PVR (low)
C4
IRIG PVR flow)
C5
X PIPA error
monitor (high)
C6
Y PIPA error
monitor (high)
C7
Z PIPA error
monitor (high)
D1
X PIPA current
monitor (low)
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3-8 POWER AND SERVO ASSEMBLY
The PSA, figure 3-8, is a group of fourteen electronic modules mounted on a
common frame. The electrical connectors and interconnecting harness are an integral
part of the frame, or header, which also functions as a heatsink for the electronic
components. Mounted to the lightweight magnesium header and filled over the modules
is the PSA cover which has a filler valve used to pressurize the unit to one atmosphere
and maintain this pressurization during the LEM flight.
The assembled unit, measuring approximately 2-5/8 inches high, 8-7/8 inches
wide and 23-1/3 inches deep and weighing approximately 20 pounds, is mounted to a
coldplate on the LEM bulkhead behind the astronaut.
The purpose of the PSA is to provide a central mounting point for the majority
of the PGNCS power supplies, amplifiers, and other modular electronic components.
Table 3-V1 lists the functions and locations of the modules contained in the PSA.
Figure 3-8. Power and Servo Assembly
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Table 3 -VI. Locations and Functions of PSA Modules
Module
Part Number
Function
Location
-28 vdc power
supply
2007107-011
Supplies power to gim-
bal servo amplifiers
and pulse torque power
supply.
izdcd n
i i nm
3200 cps,
1 percent
amplifier
2007108-011
Supplies 28 volts, 3200
cps to ducosyn trans¬
former on stable mem¬
ber.
□ □
1 m
3200 cps auto¬
matic ampli¬
tude control
(A AC), filter
and multi¬
vibrator
2007109-011
Regulates operation of
3200 cps, 1 percent
amplifier.
]□ □
m i i
800 cps,
1 percent
amplifier
2007110-011
Supplies 28 volts, 800
cps for IMU resolver
excitation. (Also sup¬
plies this power for
FDAI and SCS ref¬
erence signals. )
Provides reference
signal for two 800
cps, 5 percent ampli¬
fiers.
□
II I TT
□ I I
800 cps auto¬
matic ampli¬
tude control
(AAC), filter
and multi¬
vibrator
2007112-01:
Regulates operation of
800 cps, 1 percent
amplifier.
□
(Sheet 1 of 2)
3-18
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 3 -VI. Locations and Functions of PSA Modules
(Sheet 2 of 2)
3-19
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
3-9 LEM GUIDANCE COMPUTER
The LGC, figure 3-9, consists of two flat tray assemblies bolted together, module
sides facing. The assembled unit measures approximately 6 inches high, 12-1/2
inches wide, and 24 inches deep and weighs approximately 60 pounds. The LGC is
mounted on a coldplate on the after cabin wall (pressure bulkhead).
Figure 3-9. LEM Guidance Computer
3-20
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
CONNECTOR A5I
/
CONNECTOR A63
ffl
POWER SUPPLY MODULE A30-3I
INTERFACE MODULE A27-29
INTERFACE MODULE A27-29
INTERFACE MODULE A27-29
INTERFACE MODULE A25-26
INTERFACE MOOULE A25-26
LOGIC MODULE A24
LOGIC MODULE A23
LOGIC MODULE A22
LOGIC MODULE A2I
LOGIC MODULE A20
LOGIC MODULE A 19
LOGIC MODULE A 18
LOGIC MODULE AI7
LOGIC MODULE A 16
m
■
«
;a
■1
«
®
St
&
s»
i*
-
“
—
—
-
-
r_
.
*J
“■
_
2
2
“
_
POWER SUPPLY MODULE A30-3I
LOGIC
MODULE
AI5
LOGIC
MODULE
AI4
LOGIC
MODULE
AI3
LOGIC
MODULE
AI2
LOGIC
MODULE
A8-II
LOGIC
MODULE
A8-II
LOGIC
MODULE
A8-II
LOGIC
MODULE
A8HI
LOGIC
MODULE
A7
LOGIC
MODULE
A6
LOGIC
MODULE
A5
\ LOGIC
MODULE
A4
\ LOGIC
MODULE
A3
\ LOGIC
MODULE
A2
\ LOGIC
MODULE
Al
CONNECTOR A92
CONNECTOR A6I
CONNECTOR A62
40698
Figure 3-10. Logic Tray A
3-9.1 LOGIC TRAY A. The logic tray A assembly (figure 3-10) contains 31 modules:
24 logic, 5 interface, and 2 power supply modules. All modules are potted with a silastic
compound after being mounted on the tray.
The logic tray A assembly has three intertray connectors (A61, A62, and A63) and
two intersystem connectors on the rear. The 360 pin rear connector, A51, connects
the LGC to the main 28 vdc power source, to the DSKY, to other components of the
PGNCS, and to other LEM systems. The 144 pin rear connector, A52, provides inter¬
face with ground support equipment for LGC testing.
3-9.2 TRAY B. The tray B assembly (figure 3-11) contains 17 modules, including 6
rope modules. Eleven modules are potted into the tray in a manner similar to that in
logic tray A; the six rope modules are plug-in units located at the front of the LGC.
The tray B assembly has three intertray connectors (B61, B62, and B63) which inter¬
face with those on the logic tray A assembly.
3-21
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
I MANUAL
3-10 COUPLING DATA UNIT
The CDU, figure 3-12, consists of two tray assemblies containing a total of 34
modules. The two tray assemblies, tray X and tray S, are bolted together, module
sides facing. The unit is then mounted to a coldplate in the LEM. The assembled
unit, constructed mainly of magnesium, measures approximately 5.5 inches high,
11.3 inches wide, and 20 inches deep and weighs approximately 35 pounds.
Tray X has two connectors, one used only for component level testing; the other,
J53. used to connect the CDU to the PGNCS interconnect harness. Tray X also has a
filler valve used to pressurize the CDU.
3-22
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Figure 3-12. Coupling Data Unit
The modules in the CDU provide five separate channels to couple the LGC to the
IMU and the optical tracker. In addition to the five separate channels, the CDU contain
four modules which are shared by all channels. Basic CDU functions are as follows:
(1) Interpret commands (digital) from the LGC and convert them to IMU gimbal
positioning signals (analog).
(2) Interpret gimbal positions (analog) and transmit the information to the LGC
(digital).
(3) Couple the IMU to the FDAI.
3-23
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
(4) Interpret optical tracker azimuth and elevation angles (analog) and transmit
the information to the LGC (digital).
(5) Interpret commands (digital) from the LGC and convert them to optical tracker
positioning signals (analog).
CDU module locations are illustrated in figure 3-13 and their functions described
in table 3-VII.
3-11 SIGNAL CONDITIONER
This paragraph will give a physical description of the signal conditioner and will
be supplied when information is available.
3-12 DISPLAY AND KEYBOARD
The primary communication link between the astronauts and the PGNCS is the
DSKY (figure 3-14). The DSKY is located immediately below the lower center instrument
panel. The DSKY is approximately 8 inches high, 8 inches wide, 7 inches deep, and
weighs 17 pounds. The upper half of the DSKY is the display and the lower half is the
keyboard. The display section contains 14 caution and alarm indicators, 7 operation
display indicators, and 18 data display indicators. The words PROG, VERB, and
NOUN and the lines separating the three groups of display indicators are illuminated
whenever the PGNCS is energized, as are the 19 keys of the keyboard.
There are a 91 pin connector, a filler valve, and a power supply mounted on the
rear of the DSKY. The connector interfaces the DSKY with the LGC, other PGNCS
components, and with other LEM systems. The filler valve is used to pressurize the
DSKY to one atmosphere. The power supply provides voltages for operation of the
display indicators. The DSKY controls and indicators and their functions are listed
in table 3-VIII.
3-24
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
3-25
Figure 3-13. CDU Module Locations
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 3 -VII. Functions of CDU Modules
Module
Part Number
Function
Coarse system (5)
2007236-011
Provides coarse switching and atten¬
uation circuitry necessary to incre¬
ment angles.
Main summing ampli¬
fier and quadrature
rejection (5)
2007238-011
Provides fine switching and attenuation
circuitry necessary to increment
angles.
Quadrant selector (5)
2007243-011
Converts sin 0 and cos 0 resolver
signals to phase relationships
required by main summing
amplifier.
Read counter (5)
2007140-021
Accumulates pulses representing
angles and controls switching of coarse
system module, quadrant selector
module, and main summing amplifier.
Interrogate module
2007263-011
Generates a portion of timing pulses
required for CDU operation, pro¬
duces 14 vdc power, and provides
circuitry for data and pulse trans¬
mission.
Digital mode module
2007141-021
Provides pulse commands which are
used throughout CDU for synchro¬
nization, switching, and strobing.
Mode module
2007254-011
Buffers signals and monitors CDU
operations.
Error angle counter
and logic module (5)
2007139-021
Accumulates pulses representing
angular error and provides logic cir¬
cuitry to control operation of other
CDU modules.
Power supply
2007142-011
Supplies 4 vdc logic power to
digital logic portions of CDU.
Digital to analog
converter (5)
2007237-011
Converts digital information in
error counter into a dc analog signal
and two ac analog signals.
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
INOICATOR OLIVERS
FILLER VALVE
J9 CONNECTOR
Figure 3-14. Display and Keyboard
3-27
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
Table 3 -VIII. DSKY Controls and Indicators
Indicators and Controls
Functions
Caution and Alarm Indicators
UPLINK ACTY
Indicates information is being received via
UPLINK. (Not used for manned flights.)
ST BY
Indicates LGC is in restart condition and
low power mode.
KEY REL
Indicates that LGC wishes to display program
information and has found DSKY in use.
RESTART
Indicates LGC is in restart condition.
OPR ERR
Indicates illegal keyboard operation.
AUTO
Not used.
HOLD
Not used.
FREE
Not used.
NO ATT
Indicates that ISS is not suitable for use as
attitude reference.
TEMP
Indicates underheat or overheat condition of
IMU stable member.
GIMBAL LOCK
Indicates middle gimbal angle in excess of 75
degrees.
PROG
Indicates that program check has failed. This
indicator is controlled by the LGC program.
TRACKER
Indicates failure of LORS channel of CDU or
LORS data is not proper.
Spare
Spare.
(Sheet 1 of 3)
3-28
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 3-VHI. DSKY Controls and Indicators
Indicators and Controls
Functions
Operation Display Indicators
COMP ACTY
Indicates LGC is operating.
PROG
Indicates function or functions of current
LGC program.
VERB
Indicates verb code entered at keyboard.
NOUN
Indicates noun code entered at keyboard.
Data Display Indicators
Data display
A plus or minus sign signifies data is decimal;
indications
no sign signifies data is octal.
Keyboard Keys
KEY REL
Releases control of keyboard so that information
supplied by program action may be displayed.
ST BY
Initiates LGC restart condition and puts LGC
into low power mode. Normal operation may
be resumed by again pressing STBY.
RSET
Clears caution indicators and OPR ERR indi¬
cator.
CLR
Clears data contained in data register currently
in use.
VERB
Conditions LGC to accept next two numerical
characters as action request.
NOUN
Conditions LGC to accept next two numerical
characters as address code.
(Sheet 2 of 3)
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 3 -VIII. DSKY Controls and Indicators
Indicators and Controls
Functions
Keyboard Keys (cont)
ENTER
Informs LGC that assembled data is com¬
plete; execute requested function.
+ key
Enters positive sign for decimal data.
- key
Enters negative sign for decimal data.
0 through 9
Enter data, address code, and action request
code into LGC.
(Sheet 3 of 3)
3-30
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Chapter 4
COMPONENT THEORY OF OPERATION
4-1 SCOPE
This chapter discusses the operation of components or circuits whose operation is
not apparent in the functional descriptions presented in Chapter 2.
4-2 APOLLO II INERTIAL REFERENCE INTEGRATING GYRO
The Apollo II IRIG stabilization gyro (figure 4-1) is a fluid and magnetically sys-
pended, single-degree-of-freedom, integrating gyro. It is one of the 25 series of inertial
instruments. The 25 designation denotes the case diameter in tenths of inches. The
stabilization gyros are the sensing elements of the stabilization loop. Three such gyros
are mounted on the stable member with their input axes mutually perpendicular.
Any change in the attitude of the stable member is sensed by one or more of the gyros.
The gyros convert this displacement into an error signal which is amplified and fed
into the gimbal torque motors. The gimbal torque motors reposition the stable member
until the error signals are nulled and the original orientation of the stable member is
re-established.
The Apollo II IRIG consists of a wheel assembly, a spherical float, a cylindrical
case, a signal generator due osyn, and a torque generator ducosyn. The wheel is mounted
within the sealed float on a shaft perpendicular to the float axis and spins on pre loaded
ball bearings. The wheel is driven as a hysteresis synchronous motor in an atmosphere
of helium. The float is mounted within the case on a shaft axially coincident with the
longitudinal axes of both float and case. Precision hard-alloy pivots and bearings are
located at each end of the float shaft, with the bearing being part of the float assembly.
The torque generator ducosyn is mounted on one end of the float shaft, while the signal
generator ducosyn is mounted on the opposite end. The volume between the float and
case is filled with a suspension and damping fluid.
Four axes (input, spin, spin reference, and output) are associated with the Apollo
II ERIG. While the wheel is spinning, the gyro tends to maintain its attitude with respect
to space. If the gyro is forced to rotate about the input axis (perpendicular to the wheel
spin axis), it will respond with a torque about the output axis (perpendicular to both spin
and input axes). The spin axis is displaced from its normal or null alignment with the
spin reference axis by an amount equal to the angle through which the output axis has
rotated. The spin reference, input, and output axes are always mutually perpendicular.
4-1
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
INPUT
OUTPUT
AXIS
TORQUE
DUCOSYN
SPIN
REFERENCE
AXIS
I 569 0 A
Figure 4-1. Apollo II ERIG, Simplified Cutaway View
The rotation about the output axis in response to a rotation about the input axis in
a single-degree-of-freedom gyro is called gyroscopic precession. The output axis
is along the float shaft. Rotation of the gyro about its input axis results in a preces¬
sion of the float.
The signal generator ducosyn is mounted on the positive output axis end of the float
to provide magnetic suspension of the float with respect to the case, and to serve as a
transducer for providing an electrical analog signal which indicates the amount and
direction of the angular rotation of the float about the output axis. The torque generator
4-2
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
ducosyn is mounted on the negative output axis end of the float to provide magnetic sus¬
pension, and to serve as a transducer for converting electrical error signals to a torque
about the output axis when desired.
Since float movement is a measure of angular displacement of the gyro, friction
on the float shaft (output axis) is a critical factor of gyro sensitivity. To reduce this
friction to a negligible level, the space between the float and case is filled with a fluid
which has the same density (specific gravity) as the float. This fluid causes the float to
be suspended with respect to the case. Density of the fluid is kept equal to the density
of the float by the controlled application of heat. Heating coils attached to the Apollo
II ERIG end mounts maintain the density of the fluid. Two sensors submerged in the
fluid indicate the temperature of the fluid. The fluid also provides viscous damping of
float movement. The fluid suspension is supplemented by magnetic suspension which
keeps the pivot centered in the bearing. The magnetic suspension forces are created
by the signal and torque generator ducosyns. Under normal environmental conditions
the pivot never touches the bearing. Polished precision hard-alloy bearings and pivots
are used to minimize the friction which may result if the pivot touches the bearing under
extreme environmental conditions.
Since oxygen would rust the ferrous parts in the wheel assembly, the float is filled
with helium which will conduct heat away from the wheel motor. Because helium is a
light gas it generates little windage, resulting in the additional advantage of low windage
losses in the wheel motor. The float is filled with helium at a pressure of one-half
atmosphere to further reduce windage losses.
4-2. 1 GYRO WHEEL ASSEMBLY. The gyro wheel assembly consists of a wheel, a
shaft, hysteresis ring, ball bearings and bearing retainer. The wheel consists of a
beryllium hub with a steel rim. The purpose of the composite wheel is to concentrate
as much weight as possible in the outside rim, providing the wheel with a high moment
of inertia. The steel, hollow shaft has female threads on each end and is machined to
serve as the inner race for the ball bearings. Preloading of the wheel is achieved and
controlled by bolting the bearing retainers to the hub. The bearing retainers press on
the outer bearing race exerting a wedging action on the balls. As a result, a deliberate
load (preload) is imposed on the wheel bearing to insure that the wheel rotates precisely
at a right angle to the shaft. The amount of preload is carefully determined since ex¬
cessive preload will introduce excessive bearing friction that would limit bearing life.
The hysteresis ring, constructed of laminated, specially hardened steel, is fitted on
the wheel hub and serves as a rotor for the hysteresis synchronous motor which drives
the wheel.
4-2.2 FLOAT ASSEMBLY. The float assembly is essentially a float gimbal, two
hemispheres, hysteresis motor stator, and bearings. The wheel assembly is bolted
to the float by threaded rings. The rings also hold together the float gimbal and the
float hemispheres, both of which are made of beryllium. The hysteresis motor stator
is placed inside the float gimbal with the power leads brought out through each end of
the float gimbal. The float shaft is an integral part of the float gimbal and extends out¬
ward from the float to serve as a mount for the float bearings and ducosyn rotors. The
bearings, when placed on each end of the float gimbal, define the output axis. The float
4-3
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTIOl SYSTEM
ND-1021042
MANUAL
gimbal also has a hole fitted with a ball and screw seal through which the float is evac¬
uated and filled with helium. Preliminary balance weights are placed on the float gimbal
for rotational balancing prior to the float being inserted into the case. Balance weights
along the spin axis and the input axis are accessible from outside the case and are used
for rotational balancing after final assembly.
4-2.3 CASE. The case consists essentially of main housing and damping block assem¬
blies, end housing assembly, and main cover assembly. The float assembly is encased
in the main housing assembly and is supported with respect to the end housing by the
pivot assemblies. Beryllium damping blocks fill the space around the float. Theseblocks
provide the necessary control of the damping gap (the width of the gap between the float
assembly and case), thereby controlling the damping coefficient. The end housings are
held to the main housing by clamping caps. The end housings contain the pivot assem¬
blies, ducosyn stators, bellows to take up the expansion and contraction of the sys-
pension fluid, and a setscrew and ball seal to allow filling with the suspension fluid.
Four balance adjusters, provided in the main housing assembly, allow access to the
adjustable balance weights along the spin axis and the input axis. After hermetically
sealing and balancing the unit, the Apollo n ERIG is covered by a main cover as¬
sembly which provides a magnetic shield plus a second hermetic sealing.
4-2.4 NORMALIZING NETWORK. The normalizing network (figure 4-2) contains the
magnetic suspension capacitors, torque generator normalization resistors, temperature
sensor normalization resistor, main heater, auxiliary heater, and signal generator
preamplifier with gain normalization resistor attached. The pre-alignment package is
added to the signal generator end of the gyro case during final assembly, making the gyro
a pre-aligned gyro. The gyro is pre-aligned on a test stand with the input axis aligned
about the output axis relative to a slot in the mounting ring. This alignment is carried
over to the stable member where a pin is precisely located to pick up the slot. When the
gyro is mounted in the stable member, an additional main heater and an auxiliary
heater are placed on the torque generator end.
The signal generator preamplifier is an ac amplifier with transformer coupled input
and output which amplifies the gyro output signal prior to transmission from the stable
member to the PSA.
4-2.5 APOLLO II IRIG DUCOSYNS. The Apollo II IRIG uses ducosyns for magnetic
suspension of the float, signal generator action, and torque generator action. The
ducosyn is a separate magnetic suspension microsyn and a separate transducer microsyn
in a single unit. The unit contains two separate stators mounted in the end housing and
two separate rotors mounted on a common mounting ring of the float assembly. The
inside stator assembly consists of eight outwardly projecting tapered poles which are
wound and excited to provide magnetic suspension. The outer stator assembly consists
of twelve inwardly projecting poles which are wound to provide either signal generator
or torque generator action. The outer rotor is the transducer rotor and consists of
eight unwound salient poles. The inner rotor, which is the magnetic suspension rotor,
is cylindrical, tapered, and unwound. A beryllium ring separates the two rotors to
reduce cross -coupling effects.
4-4
SUSPENSION MODULE
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
4-5
Figure 4-2. Apollo II IRIG Normalizing Network
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
4-2.5. 1 ERIG Signal Generator Ducosyn. The signal generator ducosyn is mounted on
the positive output axis end of the gyro to provide magnetic suspension and to serve as
a transducer to provide an electrical analog signal representing the position of the float
relative to the case. (See figure 4-3). Poles 1, 4, 7, and 10 are wound with primary
windings which induce a voltage into the secondary windings on the pole pieces on either
side of the primary winding poles. All secondary windings are wound with equal turns.
The secondary windings (2-12, 3-5, 6-8, and 9-11) on either side of each primary pole
are wound in opposition to each other. When the rotor pole pieces are symmetrically
located between the pairs of secondary poles, the flux density in the secondary poles is
equal and equal voltage is induced in the secondary windings. Since the secondary wind¬
ings are wound in opposition the induced voltages cancel and the net output voltage is
zero. This is the null position of the rotor. When the rotor is rotated from the null
position as a result of float displacement, the equality of air gap reluctance is disrupted
resulting in unequal flux density in the pairs of secondary poles and therefore unequal
induced voltages in the windings. The magnitude of the net output voltage depends on the
degree of air gap reluctance unbalance; the greater the rotor displacement from null,
the greater the net output voltage. The phase of the net output voltage is determined by
the direction of rotor rotation. As a result of counterclockwise rotation, higher voltages
are induced in the secondary windings that are wound in phase with the primary windings,
causing the net output voltage to be in phase with the primary excitation. In the same
manner, clockwise rotation produces a net output voltage that is out of phase with the
primary excitation.
The Apollo II IRIG ducosyns require a 4 volt, 3,200 cps single phase excitation for
the signal generator primary windings and for the magnetic suspension portions.
4-2. 5. 2 IRIG Torque Generator Ducosyn. The Apollo II IRIG torque generator ducosyn
is mounted on the negative output axis end of the float to provide magnetic suspension
and to serve as a transducer to convert an electrical error signal into a torque about
the output axis. Figure 4-4 shows the torque generator with the rotor in the null posi¬
tion. To develop torque, current is allowed to flow through the common winding and
through either the T+ or the T- winding. The direction of torque is determined by the
winding through which current flows. The torque generator stator may be considered
as divided into four symmetrical groups of three poles. The center pole of each group
(1, 4, 7, and 10) has a common winding only and will always be a north pole when
energized. The poles on either side (2-12, 3-5, 6-8, and 9-11) of the center poles have
both T+ and T- windings with the polarity of the poles determined by which of the two
windings is energized. In either case, one pole in each group will become a north pole
and the other a south pole. Since the center pole is always a north pole, each group of
three poles will consist of two north poles and one south pole whenever the windings
are energized. The rotor will tend to align itself symmetrically between the north and
south poles, creating a torque. When the T- winding is energized, pole 12 will become
a south pole and pole 2 will become a north pole. The rotor, in attempting to align
itself, will tend to rotate clockwise until rotor pole 8 is directly opposite stator pole
12 and rotor pole 1 is directly between stator poles 1 and 2, since 1 and 2 are both
north poles. When the T+ winding is energized, stator pole 2 will become a south pole
4-6
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
GYRO
ERR
(INPUT AXIS)
SIGNAL
GENERATOR
STATOR
SUSPENSION
ROTOR
S2
SECONDARY
LO 'I
PRIMARY EXCITATION HI
SECONDARY
CENTER
SUSPENSION
.STATOR
2
PRIMARY
EXCITATION LO
BERYLLIUM
SEPARATOR
Figure 4-3. IRIG Signal Generator and Suspension Microsyn
and stator pole 12 will become a north pole. The rotor will tend to rotate counterclock¬
wise attempting to align rotor pole 2 opposite stator pole 2, and rotor pole 1 between
stator poles 1 and 12. The other poles attempt to align themselves in the same manner.
The direction of the desired torque is controlled by gyro select pulses from the
LGC. The pulses act through a switching network in the gyro calibration module to close
4-7
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Figure 4-4. IRIG Torque Generator and Suspension Microsyn
the torque current path through either the T+ or the T- winding. The magnitude of the
torque current is held constant to develop a constant torque. Torque on the rotor pro¬
duces torque on the gyro float. The resulting float displacement creates an error signal
from the ducosyn signal generator. Thus, the position of the IMU stable member is
changed by the compensating reaction from the stabilization loops.
The torque generator stator also has a reset coil and a bias compensation coil,
both of which are continuously energized by the 4 volt, 3,200 cps magnetic suspension
and signal generator excitation voltage. The reset coil serves to keep the magnetic
state of the magnetic material constant following any torque commands. This degaussing
action prevents the storage of residual magnetic dipoles in the rotor and stator which
would create torque. A winding around each group of three stator poles acts as a reset
coil for both rotor and stator. The bias compensation coil creates a torque equal and
opposite to the non-gravity torques which produce bias drift, such as the torque due to flex
leads. In this manner, the bias drift due to these sources may be reduced to zero.
4-8
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Figure 4-5. Ducosyn RLC Equivalent Circuit
4-2. 5. 3 LRIG Ducosyn Magnetic Suspension. Unit. The Apollo II IRIG ducosyn magnetic
suspension units have a tapered cylindrical rotor and tapered stator poles that develop
radial and axial magnetic suspension of the gyro float.
Each stator winding is part of a series resistance inductance capacitance (RLC)
circuit. (See figure 4-5). Although the equivalent circuit illustrated shows only two poles,
it is representative of any of the four pairs of diametrically opposed stator poles. In¬
ductances and L2 represent the total inductances of the stator windings. Resistances
Rj and R2 represent the total resistance of each stator circuit, Capacitors C^ and C2
are the external fixed capacitors in series with the resistance and inductance. The
values of and L2 vary inversely with the size of air gaps A and B respectively.
The excitation to the magnetic suspension unit is maintained at precisely 3,200
cps; the inductance is the only circuit variable. When the inductance is adjusted so the
inductive reactance equals and cancels the capacitive reactance, circuit resonance is
achieved. At resonance, the total circuit impedance is at a minimum, consisting only
of resistance, and the current is thus at a maximum. During construction and testing,
a fixed suspension capacitor is selected that develops a value of capacitive reactance
that is less than the value of inductive reactance present when the rotor is at null. The
resulting impedance allows a current flow that is less than the maximum or resonant
current. In operation, translational movement of the rotor from its null point alters
the inductance to bring the circuit closer to or further from resonance.
4-9
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The current flow through the Ri, Li, and Ci circuit of figure 4-5 increases or
decreases according to the inductance which is controlled by air gap A. At some position
of the rotor (or value of A), L will produce resonance and maximum current. As the
rotor moves in either direction from the resonant point, the current falls off sharply
because the value of L (and inductive reactance) changes to make the circuit impedance
greater. The current in the stator winding determines the amount of magnetic energy
in the stator pole. The attracting force on the rotor is equal to the change in magnetic
energy divided by the change in air gap. This relationship of force versus air gap is
such that as the rotor moves away from the stator (increasing A), the attracting force
rises to a maximum, then decreases sharply as the rotor passes through the resonant
point. A negative or repelling force is developed as the rotor is moved beyond the
resonant point. In operation, the movement of the rotor is limited by the float pivots
so the attracting force only increases as the rotor is moved away from the stator to its
maximum allowable displacement. Conversely, as the rotor moves closer to the stator,
decreasing the air gap, the attracting force decreases.
As the rotor moves left, air gap A increases and air gap B decreases, and vice-
versa. The attracting force at one stator pole changes inversely to the change in attrac¬
ting force at the other stator pole. When the rotor is displaced from its null point (where
the forces on the rotor from both poles are equal), the force from the pole the rotor is
approaching decreases, and that of the opposite pole increases. The direction of the
resultant force moves the rotor back to the null position. This action magnetically
clamps the rotor between its operating limits. Since the four pairs of stator poles are
arranged in a circle within the rotor, their simultaneous action effectively suspends
the rotor.
Since the rotor and the stator poles are tapered, end play on the float tends to in¬
crease or decrease the air gaps of the magnetic suspension units located at each end of
the float. The two magnetic suspension units act together to develop a component of
force that supports the float axially.
4-3 16 PULSED INTEGRATING PENDULUM
The 16 PIP's are used as accelerometers in the IMU. The 16 PIP in itself is not an
accelerometer, but an acceleration sensitive device. In its associated accelerometer
loop, the 16 PIP becomes an integrating accelerometer (16 PIPA).
The 16 PIP is basically a cylinder with a pendulous mass unbalance (pendulous
float) and is pivoted with respect to a case. The pendulous float has no electrical power
requirements as it is completely mechanical in operation. The space between the pen¬
dulous float and case is filled with a fluid. A signal generator ducosyn, located at one
end of the float, provides magnetic suspension of the float with respect to the case and
acts as a transducer to convert mechanical rotation of the float with respect to the case
into electrical analog signals. A torque generator ducosyn, located at the other end of
the float, provides magnetic suspension of the float with respect to the case and acts as
a transducer to convert electrical signals into mechanical torque about the float
shaft. A 2 volt rms, 3,200 cps, single phase excitation is required for the magnetic
4-10
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MANUAL
suspension portion of each ducosyn and for the transducer portion of the signal gen¬
erator ducosyn.
The output axis of the 16 PIP is defined by the axis of the pivots which support the
float with respect to the case. (See figure 4-6.) The pendulum axis is defined by a line
which passes through the mass unbalance and intersects the output axis at a right angle.
The input axis is the axis along which the 16 PIP is sensitive to acceleration. The input
axis and pendulum axis form a plane that is perpendicular to the output axis. When the
float rotates about the output axis, the pendulum axis is displaced proportionately from
its normal or null position (pendulum reference axis). The pendulum reference, input,
and output axes are always mutually perpendicular.
The mass unbalance hangs below the output axis and is forced by loop torquing to
swing like a pendulum. The torquing required to keep the pendulum action oscillatory
at no acceleration is a known value. When acceleration is sensed along the input axis,
an additional torque is felt by the pendulum and the loop compensates for the accelera¬
tion torque by supplying torquing current for additional time.
Figure 4-6. Definition of 16 PIP Axes
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Figure 4-7 illustrates the direction the pendulous mass tends to swing due to
acceleration torque as viewed from the positive end of the output axis or signal gen¬
erator end of the PIP.
Acceleration in the direction of the positive input axis (the direction in which the
arrowhead points) results in a torque on the float about the output axis which tends to
rotate it in the negative angular direction (-0 OA) about the output axis. Conversely,
acceleration in the direction of the negative input axis produces a torque on the float
tending to rotate it in the positive angular direction (+ 0 OA) about the output axis. When
no acceleration is being felt along the input axis, the summation of the angular dis¬
placement about the output axis is zero; and by definition, the PIP is at a null.
Maximum sensitivity and linearity of the 16 PIP occur near null. To assure maxi¬
mum sensitivity and linearity, the accelerometer loop in which the 16 PIP is used
restricts the angular displacement about the output axis to very small excursions in
either direction from null. The accelerometer loop is designed so that the torque
developed by the torque generator is equal to and opposite the pendulous torque result¬
ing from applied acceleration. The signal generator, located at the positive end of the
output axis, senses an angular displacement of the float about the output axis. The phase
and magnitude of the output signals from the signal generator secondary winding are
determined by the direction and amount of float displacement. The error signals are
PNA
t
Figure 4-7. Result of Acceleration Along Input Axes
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MANUAL
processed by the accelerometer loop into incremental velocity pulses to the LGC and
intotorquing current to the torque generator.
4-3. 1 FLOAT ASSEMBLY. The float is a hollow beryllium cylinder fitted with a shaft
on which the float pivots are located. On both ends of the float are salient four pole
transducer rotors and cylindrical magnetic suspension rotors with tapered inside dia¬
meters. The rotor itself is a solid one piece device. The pendulous mass screws into
and protrudes slightly from the float. A pin and screw which provides pendulousity ad¬
justment also serves as a stop to limit float rotation about the output axis to ±1 degree.
Adjustable balance weights for rotational balancing of the float are located along the
pendulum axis and the input axis. The completed float assembly is placed in a main
housing assembly filled with a suspension fluid. The suspension fluid provides fluid
suspension of the float with respect to the case and viscous damping of the float.
4-3.2 HOUSING ASSEMBLY. The housing assembly consists of a mainhousing assem¬
bly and two end housings. Damping blocks line the inner diameter of the main housing
so as to surround the float. Four bellows assemblies are located within the damping
blocks and take up the expansion and contraction of the suspension fluid resulting from
variations in fluid temperature. Each end housing contains a pivot bearing, an eight
pole magnetic suspension stator, and either an eight pole signal generator stator
or an eight pole torque generator stator. The two end housings are called the signal
generator end housing (on the +OA end) and the torque generator end housing (on the -OA
end). The magnetic suspension microsyns have tapered stator poles and a tapered rotor,
developing magnetic suspension forces in both radial and axial directions.
4-3.3 OUTER CASE ASSEMBLY. The housing assembly is completely covered by an
outer case which provides magnetic shielding and a hermetic seal for the unit. Heating
coils are placed between the mainhousing and the outer case to heat the suspension fluid
to the proper temperature for fluid suspension of the float. All electrical connections for
signal generator, torque generator, magnetic suspension microsyns, and heaters are
brought out through the torque generator end of the case.
4-3.4 NORMALIZING NETWORK. The 16 PIP normalizing network module contains
the suspension capacitors, torque generator normalizing resistors, and temperature
sensor normalizing resistors. This module is mounted over the 16 PIP and bridges
the 16 PIP end cap. However, to avoid PIP alignment problems, the module is fas¬
tened to the stable member instead of the PIP.
4-3.5 PIP DUCOSYNS. The 16PIPducosyn signal generator and torque generator differ
from the Apollo n IRIG units in both construction and operation. The 16 PIP signal gen¬
erator and torque generator have eight pole stators. The 16 PIP ducosyn rotor is con¬
structed from a solid piece of ferrite. Flats are ground onto the outer diameter of the
rotor to create pseudo salient poles which serve as the transducer rotor. The inner
diameter of the rotor is tapered and serves as the magnetic suspension rotor. There is
no magnetic separation between the transducer rotor and the suspension rotor which
allows the magnetic suspension rotor to degauss the torque generator rotor. The de¬
gaussing prevents the storage of residual magnetic poles in the magnetic material which
could cause unwanted torques to be created.
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The torque generator stator has a single winding per pole. (See figure 4-8.) The
windings on the even poles develop negative torque and the windings on the odd numbered
poles develop positive torque. The accelerometer loop applies constant dc current to
either the odd or even poles. The torque generator stator also has a reset winding which
degausses the stator thus preventing the storage of residual magnetic poles which could
create unwanted torque.
The signal generator stator poles have both a primary and secondary winding per
pole. The secondary windings are wound in opposition so that when the rotor is at null
the air gap reluctance at each pair of stator poles is equal and the net output voltage is
zero. When the rotor is displaced from null, the air gap reluctance becomes unequal
and a net output voltage proportional to the direction and magnitude of the float displace¬
ment is developed. The output of the signal generator is amplified, phase shifted, and
applied to the interrogator module in the accelerometer loop which detects the direction
of float displacement.
TORQUE CURRENT
RETURN
15636
Figure 4-8. PIP Torque Generator
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4-4 COUPLING DATA UNIT
The CDU is an electronic device used as an interface element between the PGNCS
subsystems, and between the PGNCS and various LEM displays and controls. The CDU
is a sealed unit containing 34 modules of ten types. The ten module types make up five,
almost identical, loops; one each for the inner, middle, and outer gimbals and one
each for the optical tracker azimuth and elevation axes. Several of the CDU modules
are shared by the five loops.
The CDU functions primarily as an analog to digital converter and as a digital to
analog converter. The analog to digital converter converts resolver signals into digital
information which is stored in a 16 stage binary counter called the read counter. The
digital information is also transmitted to the LGC in the form of pulses. The digital
to analog converter accepts pulses from the LGC, stores them in a nine stage binary
counter called the error counter, and provides ac and dc output signals proportional to
the stored pulses. A digital feedback path between the read counter and the error counter
is provided to count the error counter up as the read counter counts down and vice
versa.
The CDU converts the angular information from IX and 16X resolver signals
(sin 6, cos0, sin 16 0, and cos 16 0) into digital information. The resolver angle is
digitalized into bits, equal to 20 arc-seconds each and stored in the read counter. An
error signal proportional to the difference between resolver angle and the CDU angle
(the angle registered by the read counter) causes the read counter to count until the
error signal is nulled. If the difference between the resolver angle (0) and the CDU
angle ( ip) is greater than 0.1 degree, the read counter will be incremented at a 12.8
kpps rate. The incrementing rate will be 800 pps if the difference is less than 0.1
degree.
4-4.1 COARSE SYSTEM MODULE. The coarse module functions with the read counter
to form the coarse analog to digital conversion system. The coarse module receives
the sin 0 and cos 0 signals from the IX gimbal angle resolver and switches them
through attenuation resistors which represent various values of sin j/j and cos ip. The
resolver angle is compared with the angle registered by the read counter through the
mechanization of the following trigonometric identity:
± sin (0-1 /)) = ± sin 0 cos ip± cos 0 sin ip
where 0 is the gimbal angle and ip is the CDU angle represented by the accumulation
of bits registered by the read counter. The value of ip can be considered as the gimbal
angle as indicated by the read counter. When 0 and i p are equal, the equation goes
to zero. If 0 does not equal ip , an error detector in the coarse module will produce
an output which will cause incrementing pulses to be sent to the read counter. As the
read counter counts up or down, changing the value of ip, it sends switch control pulses
from its seven most significant stages to the coarse module. The switch control pulses
operate switches in the coarse module which change the arrangement of the attenua¬
tion resistors to obtain different values of sin ip and cos ip in order to obtain a null
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MANUAL
output from the error detector. For each read counter angle 0, there is a corre¬
sponding switch arrangement which will produce a null.
The accumulation of 0, the read counter indicated gimbal angle, is controlled by
three modules within the CDU: the coarse module, the main summing amplifier and
quadrature rejection module (MSA & QR), and the quadrant selector module. The
coarse module is used in conjunction with the IX gimbal angle resolver inputs. The
other two modules are used in conjunction with the 16X gimbal resolver inputs and
function with the read counter to form the fine analog to digital conversion system.
Figure 4-9 illustrates the mechanical angles of the gimbals, the read counter
bit positions associated with the mechanical angles, and the coarse and fine system
switching associated with each of the read counter bit positions. Note that bits 2°
through 2*1 are associated with fine system switching and bits 2^ through 2*5 are
associated with coarse system switching. The three bit overlap of the coarse and fine
systems provides a smooth transition from one system to the other. The angles above
the read counter blocks are the mechanical angles through which the IX gimbal angle
resolver shaft rotates. Note also that 180 electrical degrees of 16X resolver rotation
is equal to 11.25 degrees of IX resolver angle.
MECHANICAL ANGLE 100* 90* 45* 225* II-25* 5.6* 2£* 1.4* 0.7* .35* .17* X38‘ .04* .02* 40" 20"
16182
Figure 4-9. Read Counter Relationship to Coarse and Fine System Switching
Figure 4-10 provides a functional block diagram of the coarse module. The IX
resolver output signals, 26 v (rms) sin 0 and 26 v (rms) cos 0 , are applied through
transformers which have a transformation ratio of 26:4. A 28 v (rms) 800 cps
reference signal is applied through a transformer which has a transformation ratio
of 28:4. The maximum voltage available at the transformer secondaries, high to cen¬
ter tap, is 4 v (rms). The gimbal angle is represented by the amplitude of the sin 0 and
cos 0 signals and by their phase with respect to the 800 cps reference signal. If the
4-16
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
SI2 (.049)
COARSE TERNARY
LEVEL (C|) TO
EC 8 L MODULE
AMBIGUITY
DETECT (Ad)
16153 A
Figure 4-10. Coarse System Module, Block Diagram
gimbal angle were 150 degrees, for example, the sin 0 and cos 0 signals at the trans¬
former secondaries would be equal to:
(1) (4 v rms) (sin 150°) =
(4 v rms) (0.5)
(2) (4 v rms) (cos 150°)
(4 v rms) (-0.866)
2.0 v (rms)
-3.46 v (rms)
The sin 0 signal would be in phase with respect to the 800 cps reference. The cos
0 signal would be out of phase with respect to the 800 cps reference, as is signified
by the minus sign. Figure 4-11 shows the phase relationship of the IX resolver
sine and cosine output signals with respect to the 800 cps reference.
The center tapped secondary of the transformers provides both an in phase and an
out of phase signal of equal amplitude, as signified by the plus or minus sign shown
on each portion of the secondary winding. (See figure 4-10.) Thus if the cos 150 degrees
signal, previously mentioned, were to be taken from the out of phase secondary,
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MANUAL
180°
90°
SINE +
COSINE—
SINE +
COSINE +
SINE-
COSINE-
SINE —
COSINE +
270°
+ INDICATES ELECTRICAL OUTPUTS IN PHASE WITH THE REFERENCE
- INDICATES ELECTRICAL OUTPUTS OUT OF PHASE WITH THE REFERENCE
16134
Figure 4-11. Resolver Sine and Cosine Phase Relationships
the signal would be equivalent to (-4 v rms) (-0.866) = 3.46 v (rms), and would be in
phase with respect to the 800 cps reference. The minus sign in front of the 4 v (rms)
signifies that the out of phase portion of the transformer secondary was used. The
signal from each portion of the T2 and T3 secondary windings is applied to two tran¬
sistorized switches. The circuit for one of the switches, SI, is shown in figure 4-12.
The circuit consists of switching transistor Q2 and the transistor driver Ql. When
the logic equation for switch control signal DC1 isn't satisfied, DC1 is at a positive
voltage level allowing Ql to conduct to saturation and thus keep the base of Q2 grounded.
With its base grounded, Q2 is turned off (or open) preventing the transformer output
signal from being applied to the attenuator resistor circuit labeled cos 22.5°. When
its logic equation is satisfied, DC1 drops to 0 vdc, Ql stops conducting which allows
the base of Q2 to rise toward -*-28 vdc causing Q2 to conduct to saturation. With Q2
turned on, the transformer output is applied through the attenuator resistor circuit
to the summing junction of operational amplifier Al. All of the coarse system module
switches (SI through S12) operate in an identical manner. The logic equations for the
switch control signals (DC1 through DC12) that activate the switches are also given
on figure 4-12.
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MANUAL
TO SUMMING
JUNCTION OF
A|.
16155
DCl =
2,S2H 2>3-
2,5214213
DC7 -
2,5,2,4213.
214213)
DC2
215 214 2*3 .
2152,4213
DC8
215 «214 213 •
2,4213)
DC3 =
2152M213.
215 2* 213
DC9
2* 2
DC-1 =
2152H213-
215 214 21 3
DC10
2* 1
DC5
213 ( 21 4 213
. 7^
DCl 1
210
DC6
2,5<2,4213
. 2,4213)
DC 12
29
Figure 4-12. Coarse Switch Circuit and Logic Equations
Switches SI through S8 mechanize the systems nulling identity, ± sin (0-0) =
± sin 0 cos 0 ± cos 0 sin 0, directly by switching the sin 0 and cos 0 signals from
the transformer secondaries through the attenuator resistors which represent values
of sin 0 and cos 0 . At the same time the switches select either the in phase, or
out of phase transformer output so that the attenuated signals will always be out of
phase with respect to each other at the summing junction and thus be consistent with
the requirements of the nulling identity. To develop the signal equivalent to the
sin 0 cos 0 term of the identity, a single switch from the SI through S4 group of
switches will be closed to select either the in phase or out of phase sin 0 signal
and connect it to an attenuator resistor circuit representing either cos 22.5 degrees
or cos 67.5 degrees. The cos 0 sin 0 signal is developed in the same manner by
a single switch in the S5 through S8 group. The transformer outputs selected in each
case will cause the sin 0 cos 0 and the cos 0 sin 0 signals to be out of phase with
respect to each other at the summing junction. When the two attenuated signals are
summed together at the summing junction, a difference or resultant voltage is devel¬
oped which represents the sin (0-0) side of the identity. The SI through S8 switches
can select values of 0 to match the gimbal angle to within 22.5 degrees. The result¬
ant voltage, therefore, may be a maximum of (±4 v rms) (sin 22.5°) = ±1.53 v (rms).
The resultant voltage can be nulled out by summing it with voltage increments of
proper phase supplied by the voltage ladder formed by switches S10, Sll, and S12.
The ladder, in effect, performs a linear interpolation to match the difference angle
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MANUAL
(0- 0) to within 2. 8 degrees in steps of 2.8 degrees. The ladder switches are activated
by switch control signals from the 29, 210, and 211 stages of the read counter. The
signal input to the ladder switches is from the out of phase secondary of the 800 cps
reference transformer T3. The remaining switch, S9, is controlled by the 212 stage
of the read counter and supplies an in phase reference signal to the summing junction.
The operation of the S9 switch will be discussed in more detail later.
The coarse system switches activated at any particular gimbal angle can be deter¬
mined by first determining what read counter stages will have accumulated bits (see
figure 4-9) and applying this information to the logic equations given in figure 4-12
to determine what switch control signals will be generated. A simpler and more
convenient method is provided by the coarse switching diagram given in figure 4-13.
R.+C67. 5
+C67.5 +S67 5 4C675
Figure 4-13. Coarse Switching Diagram
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
The coarse switching diagram illustrates the range of gimbal angles over which each
switch is closed. The S and C designations indicate a sine and cosine attenuator
resistor, respectively, with the value of the attenuator resistor given after the desig¬
nator. The plus and minus signs signify the polarity of the transformer secondary
the attenuator resistor is connected to. The R designation indicates the closure of
switch S9. The L designation indicates the closure of one or more of the ladder
switches.
A gimbal angle which illustrates the operation of switches SI through S8 is 67.5
degrees. A gimbal angle of 67.5 degrees (45° + 22.5°) places a bit in read counter
stages 2*2 and 2*3 (see figure 4-9) and satisfies the logic equations for DC4 and DC6
(see figure 4-12), which close switches S4 and S6. The coarse switching diagram
verifies the closure of a +C67.5 and a -S67.5 switch which correspond to switches
S4 and S6. The voltages present at the summing junction as a result of the closure of
switches S4 and S6 are:
(S4) (4 v rms ) (sin 67.5°) (cos 67.5°) =
(4 v rms ) (0.924) (0.383) = 1.42 v rms
(S6) (-4 v rms) (cos 67.5°) (sin 67.5°) =
(-4 v rms) (0.383) (0.924) = -1.42 v rms
The two voltages are equal in amplitude but opposite in phase and therefore cancel
and a null is accomplished.
A gimbal angle which illustrates the use of the ladder is 28.1 degrees. A gimbal
angle of 28.1 degrees (22.5° + 5.6°) places a bit in read counter stages 212 and 210
satisfying the logic equations for DC 3, DC 5, and DC 11 which close switches S3, S5,
and ladder switch Sll, respectively. The coarse switching diagram verifies that switch
S3 (+ cos 22.5°), S5 (-sin 22.5°), and the ladder are actuated. The voltages present
at the summing junction as a result of the closure of switches S3 and S5 are:
(S3) (4 v rms ) (sin 28.1°) (cos 22.5°) =
(4 v rms ) (0.471) (.924) = 1.74 v rms
(S5) (-4 v rms) (cos 28.1°) (sin 22.5°) =
(-4 v rms) (0.882) (.383) = -1.35 v rms
The resulting in phase voltage from the S3 and S5 closure is 0.39 v (rms). To null
the system, this in phase voltage must be summed with an out of phase signal. With
ladder switch Sll closed, an out of phase voltage equivalent to (-4 v rms) (sin 5.62) =
-0.39 v (rms) is applied to the summing junction to establish a null.
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When the resultant signal at the summing junction due to the switch closures in the
SI through S8 group of switches is an out of phase voltage, operation of the ladder
switches, which always provide out of phase voltages, will aggravate the unnulled
condition. An in phase signal is required at the summing junction with which the
ladder signals can be summed to obtain a null. This required in phase signal is
provided by switch S9 and the + reference side of transformer T3 as shown on figure
4-10. Switch S9 is activated on alternate 22.5 degree segments, as shown on the
coarse switching diagram, because it is in those segments that switches SI through
S8 can produce an out of phase resultant. Switch S9 provides a signal equivalent
to (4 v rms) (sin 22.5) = 1.53 v (rms) which, in effect, inverts the out of phase re¬
sultant to an in phase signal so that the out of phase ladder signals can accomplish
a null. Expressing the function of switch S9 in another way would be to say that it
creates the effect of a 22.5 degree shift in gimbal angle.
A gimbal angle which would illustrate the use of switch S9 as well as the ladder
is 239.1 degrees. A gimbal angle of 239.1 degrees (180° + 45° + 11.25° + 2.8° =
239.05°) places a bit in read counter stages 215, 2*3, 21*, and 2 . Bits in these
positions satisfies the logic equations for DC2, DC8, DC 10 and DC 12, closing switches
S2, S8, S10, and S12. The absence of a bit in read counter stage 2 ^ satisfies the logic
equation for DC 9 which closes switch S9. The sine and cosine of 239.1 degrees are
both negative since the angle lies in the third quadrant. The voltages present at the
summing function as a result of switches S2 and S8 being closed are:
(S2) (-4 v rms) (-sin 239. 1°) (cos 67.5°)
(-4 v rms) (-.8581) (.383)
(S8) (4 v rms ) (-cos 239. 1°) (sin 67.5°)
(4 v rms ) (-.5135) (.924)
1.35 v (rms)
-1.90 v (rms)
The resultant out of phase voltage from the S2 and S8 closure is -0.55 v (rms). It can
be seen that summing this voltage with the out of phase voltages from the ladder
switches S10 and SI 2 will increase the out of phase resultant at the summing function.
The closure of sjvitch S9, however, provides the necessary in phase voltage- value to
obtain a null. Summing the in phase S9 voltage with the out of phase resultant provides
a new resultant of 1.53 - 0.55 = 0. 98 v (rms). The voltages present as a result of the
S10 and S12 closures are:
(S10) (-4 v rms) (sin 11.25°)
(-4 v rms) (1.95)
(S12) (-4 v rms) (sin 2.8°)
(-4 v rms) (.049)
-0.78 v (rms)
-0.20 v (rms)
4-22
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MANUAL
Summing the total ladder signal with the S2, S8, and S9 resultant (0.98- 0.98 = 0 v rms)
establishes a null.
In order for the system to be nulled, the voltage at the summing junction of ampli¬
fier Al, must be low enough to keep the amplifier output (E out = E in x gain) below the
triggering level of the schmitt trigger error detector. The amplifier output is referred
to as the coarse error signal. When the system is not nulled, the coarse error is
large enough (1.33 volts peak-peak nominal) to cause the error detector to fire and to
generate an 800 cps square wave output. The 800 cps output, referred to as the
coarse ternary level signal (Ci), is sent to the read counter logic section of the error
counter and logic module. The coarse ternary level will exist when the error (0-0)
is greater than approximately 5 degrees. The logic within the error counter and logic
module sends pulses at 12.8 kpps to count the read counter up or down. If the coarse
ternary level signal is out of phase with respect to an 800 cps square wave reference
signal in the logic, the logic causes the read counter to be counted down and in like
manner counts the read counter up if the coarse ternary level signal is in phase.
The read counter, in turn, will change the configuration of the coarse system switches,
choosing different attenuation values (sin 0 and cos 0) until 0=0 and the system is
nulled. The coarse error signal is also supplied to the mode module fail detect cir¬
cuits where it is monitored and to the CDU test point connector for external monitoring
purposes. The coarse system module also performs two additional functions: generates
the ambiguity detect signal (Ad) and the IMU cage signal. The IMU cage signal is
taken from a separate secondary winding of the sin 0 transformer T1 and is used
during the IMU cage mode to drive the gimbals to their zero positions. To develop the
ambiguity detect signal, the output of a separate secondary winding on the cos b trans¬
former, T2, is applied through an emitter follower to a schmitt trigger which fires
when its input exceeds a nominal value of approximately 6 volts (p-p). The schmitt
trigger output is an 800 cps square wave, which will exist when the gimbal angle is
between 125 degrees and 235 degrees. The ambiguity detect signal is sent to the
ambiguity logic circuit in the digital mode module to indicate the possibility of a false
or ambiguous gimbal angle.
4-4.2 QUADRANT SELECTOR MODULE. The quadrant selector module functions with
the MSA & QR and with the read counter module to form the fine analog to digital
conversion system. The quadrant selector module inverts the 16X resolver sine or
cosine signals as necessary, depending on the quadrant the resolver angle lies in, so
that they are always out of phase with respect to each other. A second function of the
quadrant selector module is the generation of an 800 cps reference signal.
In order to implement the nulling identity,
± sin (0-0) = ± sin 0 cos 0 ± cos 0 sin 0
for the fine analog to digital conversion system, the sin 0 and cos 0 signals from
the 16X gimbal angle resolver must be switched so that they are always out of phase
with respect to each other. Figure 4-11 shows that the resolver signals are out of
phase with each other only in quadrants II and IV. The quadrant selector will invert
4-23
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MANUAL
the sin 0 signal in quadrants I and IV, and invert the cos 0 signal in quadrants HI
and IV. Figure 4-14 is a block diagram of the quadrant selector module. The switch
driver circuits and associated switch control signals which operate the various quadrant
selector switches are not shown.
The inversion of the sin 0 signal is accomplished by operational amplifiers A1
and A2 and switches S5 and S6 in the following manner. Switch S6 is closed and S5 is
opened to provide a feedback path around A2 through R9 and to disconnect the output
of A2 from the input of Al. The sin 0 signal, applied to A1 through Rl, is inverted
by the normal operation of Al and the desired inverted sin 0 signal is made avail¬
able at its output. When no inversion is required, the switch configuration is changed
to S5 closed and S6 opened. The feedback path around A2 is closed through R4 and the
output of A2, which is also inverted, is applied to the input of Al through R2. Since
the resistance of R2 is half that of the feedback resistor of Al, an inverted sin 0 signal
of twice normal amplitude is applied to the summing junction input of Al. When this
signal is summed with the in phase sin 0 signal from Rl, the resultant signal is an
inverted sin 0 signal of normal amplitude. The inverted sin 0 signal is again inverted
by Al to re-establish an in phase sin 0 signal at its output.
Switches S5 and S6 are closed when the following logic equations are satisfied:
55 = 210 211 + 210 211
56 = 210 211 + 210 211
The 211 stage of the read counter corresponds to 180 electrical degrees in the fine
system and the 210 stage corresponds to 90 electrical degrees. The logic equations
then state that S5 is closed when the angle 0 is between 90 degrees and 180 degrees
(210 2H) or between 180 degrees and 270 degrees (210 2ll) which are the II and in
quadrants, respectively. S6 is closed when 0 is between 270 degrees and 360 degrees
(210 2ll) or between 0 degrees and 90 degrees (21$ 2ll) which are the IV and I
quadrants, respectively.
Phasing of the cos 0 signal is performed in the same manner as the sin 0 signal
using A3, A4, S7, and S8. The cos 0 signal is inverted in the III and IV quadrants.
The logic equations for S7 and S8 are:
57 = 211
58 = 211.
S8 will be closed and S7 will be open when j/j is between 180 degrees and 360 degrees
(211) providing an inverted cos 0 signal at the output of A3. S7 is closed and S8 is
open when 0 is between 0 degrees and 180 degrees (2il) providing a non-inverted
signal at the output of A3. Figure 4-15 illustrates which of the S5 through S8 group
of switches are closed over the various segments of 360 electrical degrees of 16X
resolver rotation.
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
REFERENCE DESIGNATIONS
CORRESPOND TO SCHEMATIC
2010059.
1 6 1 8 1
Figure 4-14.
Quadrant Selector Module, Block Diagram
4-25
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MANUAL LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
Figure 4-15. Fine Switching Diagram
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Switches SI through S4 select resistance values located in the MSA & QR which
attenuate the properly phased sine and cosine signals at the inputs of the MSA & QR.
The accumulation of bits in the twelve least significant stages of the read counter
controls all switches in the fine system. At any angle, one and only one switch of the
four (SI through S4) is on, selecting the appropriate value of attenuation. The values
of attenuation selected by each switch is given below:
(51) sin 11.25 degrees and cos 11.25 degrees
(52) sin 33.75 degrees and cos 33.75 degrees
(53) sin 56.25 degrees and cos 56.25 degrees
(54) sin 78.75 degrees and cos 78.75 degrees
If the resolver angle 0 were equal to any of the exact values given above or to quad¬
rature multiples, a null would be accomplished at the summing junction of the main
summing amplifier in the MSA & QR module without the benefit of any additional
signals. As an example, assume an angle of 213.75 degrees (equivalent to 33.75 degrees)
exists at the resolver. The sin 213.75 degree signal is a negative quantity (out of
phase) as is the cos 213.75 degree signal. The sine is not inverted in quadrant in
and therefore remains as an out of phase voltage. The cosine is inverted in quadrant
III and the out of phase cos 213.75 degree signal becomes an in phase voltage. At
this value of 0 , switch S2 will be closed and the result at the main summing junc¬
tion would be:
(sin 213.75°) (cos 33.75°) - (cos 213.75°) (sin 33.75°) = 0
and the desired null would be accomplished. If the resolver angle is not equal to
any of the attenuation values, or their quadrature multiples, the required attenuation
cannot be accomplished by switches SI through S4 alone. Additional switching is then
performed in the MSA & QR module ladder circuits. The logic equations mechanized
to control the operation of switches SI through S4 are as follows:
SI
n
to
00
29
2io
+
28
29
21°
S2
= 28
29
2io
+
28
?
7°
S3
= 2s
29
210
+
28
29
2To
S4
= 2®
29
210
+
28
29
2To
Figure 4-15 illustrates which of the SI through S4 switches are closed over the various
segments of 360 electrical degrees of 16X resolver rotation.
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Switches SI through S4 also select attenuation values at the inputs of the sine
and cosine amplifiers for use in generating an 800 cps reference signal. In obtaining
a null at the main summing amplifier, it is necessary to supply a reference signal to
the ladder network that is in phase with respect to the external 800 cps reference input
of the resolver. This reference is equivalent to cos (0- 0) and is generated in the
quadrant selector module by solving the trigonometric identity:
cos (6-0) = sin 0 sin 0 + cos 0 cos 0
The reference identity is mechanized by the sine amplifier A5, the cos amplifier A6,
and switches S9 through S14. The reference identity implies that the sine and cosine
signals from the resolver must always be in phase with respect to each other, in con¬
trast to the nulling identity which required the signals to be out of phase with respect
to each other. In solving the reference identity it is necessary to re-phase the sine
and cosine signals so that they are always in phase and consistent with the equation.
The inputs to the sine amplifier are the attenuated sin 0 signals from switches SI
through S4, the values of which are sin 0 sin 11.25°, sin 0 sin 33.75°, sin 0 sin 56.25°,
and sin 0 sin 78.75°, respectively. The inputs to the cosine amplifier are the attenuated
cos d signals from switches SI through S4, the values of which are cos 0 cos 11.25°,
cos 0 cos 33.75°, cos 0 cos 56.25°, and cos 0 cos 78.75°, respectively. It should be
remembered that only one of the four switches can be closed at any particular time and
the sine and cosine signals are always out of phase with respect to each other at the
inputs to the sine and cosine amplifiers.
The sine and cosine amplifiers each have two outputs which may be switched to
the ladder amplifier in the MSA & QR module but the switching logic allows the selec¬
tion of only one of the four outputs at any particular time. Switch Sll switches the out¬
put of the sine amplifier to the input of the cosine amplifier and S14 switches the
output of the cosine amplifier to the input of the sine amplifier. Switches Sll and
S14 are never closed at the same time. Switch Sll is closed when the angle 0 is in
quadrant I or ID; switch S14 is closed when the angle 0 is in quadrant II or IV. Both
the sine and cosine amplifiers invert their input signals. The effect is to have one
amplifier invert the SI through S4 input signal that is out of phase with respect to the
external 800 cpss reference, sum it with the in phase SI through S4 signal and invert
the resultant signal to an out of phase signal at the output of the second amplifier.
Switches S9 and S10 switch the sine amplifier outputs to the ladder amplifier and switches
S12 and S13 switch the cosine amplifier outputs to the ladder amplifier. Switches S9
and S10 alternate on and off every 11.25 degrees in the second and fourth quadrants (at
which time S14 is closed) and switches S12 and S13 alternate on and off in the first and
third quadrants (at which time Sll is closed). One output, therefore, is always present
at the input to the ladder amplifier. The output signal switched to the ladder amplifier
is always out of phase with respect to the external reference and when it is inverted
by the ladder amplifier it becomes the in phase cos (0-0) reference signal required
at the ladder network. The cos (0-0) signal is of approximately constant amplitude
for all inputs to the cos (0-0) generator circuit.
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The logic equations mechanized to control the switching in the cos (0- 0) generator
are as follows:
S9 =
2? 210
S12
= 27 210
S10 =
27 210
S13
= 27 210
Sll =
2i°
S14
= 210
Figure 4-15 illustrates the operation of these switches through 360 electrical degrees
of 16X resolver rotation.
The switches that connect the sine or cosine amplifier outputs to the ladder ampli¬
fier also connect these outputs to attenuator resistors at the main summing junction
of the main summing amplifier to establish at the junction either a bias signal or an
out of phase reference signal corresponding to -11.25 degrees. Switches S9 and S12
provide inputs to the -11.25 degree attenuator resistor. This signal, which is referred
to as the -11.25 degree bit, performs a function similar to that performed by the sig¬
nal from switch S9 in the coarse module. Switches S10 and S13 provide inputs to the
bias attenuator. The bias signal, also referred to as a AK signal, is applied to the
summing junction to minimize any error generated by the implementation of the
cos (0-0) equation. Both the -11.25 bit and the bias signal are further discussed in
the MSA & QR module discussion.
4-4.3 MAIN SUMMING AMPLIFIER AND QUADRATURE REJECTION MODULE. The
MSA & QR module functions with the quadrant selector module and the read counter
module to form the fine analog to digital conversion system. The MSA & QR performs
three functions: summing, quadrature rejection, and generation of the Fi and F2
ternary level signals. A block diagram of the MSA & QR module is given in figure
4-16.
In the summing operation, the signals from the quadrant selector module are
summed at the main summing junction with the output of the ladder network and the
output of the quadrature rejection circuit. The signals from the quadrant selector
module are the two signals supplied through the operation of switches SI through S4
that are always out of phase with respect to each other and, secondly, either the
-11.25 degree bit signal or the bias signal from amplifiers A5 or A6. Both the -11.25
degree bit signal and the bias signal are out of phase with respect to the 800 cps
reference. If a gimbal angle 0 exists that is not an exact multiple of 11.25 degrees,
the main summing junction cannot be nulled by the operation of switches SI through
S4 alone. If this condition exists, an in phase signal from the ladder amplifier is
supplied through switches S15 through S21 to null the signal at the main summing
junction. Switches S15 through S21 are controlled by the accumulation of bits in the
2 through 2 stages of the read counter. The in phase signal from the ladder network
is the cos (0-0) reference generated in the quadrant selector module and inverted
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
4-30
Figure 4-16. Main Summing Amplifier and Quadrature Rejection Module, Block Diagram
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
by the ladder amplifier. The result of the summation of these signals, with the aid
of the quadrature rejection circuit, is about a six millivolt rms null at the output
of the main summing amplifier.
To illustrate the summing operation, assume the angle registered by the read
counter, 0 , is between 0 and 11.25 electrical degrees. Since the angle lies in the first
quadrant, the in phase and relatively small sin 0 signal is inverted by the quadrant
selector and is attenuated by a factor equivalent to cos 11.25 degrees at the main
summing junction. The in phase and relatively large cos 0 signal is attenuated by a
factor equivalent to sin 11.25 degrees at the main summing junction. The resultant
voltage of these two signals from the quadrant selector is an in phase voltage which
must be summed with an out of phase voltage to obtain a null. If the in phase voltage
from the ladder switches were summed with the in phase resultant from the quadrant
selector signals, the in phase resultant would be increased, aggravating the unnulled
condition. The out of phase voltage necessary to accomplish a null is provided by the
-11.25 degree bit signal. The effect of this signal is to invert the resultant from the
quadrant selector signals to an out of phase voltage which may be nulled out with
increments of in phase voltage from the ladder. The -11.25 degree bit signal per¬
forms the same function as the S9 reference signal in the coarse system module.
If 0 is between 11.25 and 22.50 electrical degrees, quadrant selector switch S12
is open and S13 is closed which removes the -11.25 degree bit signal and applies
the bias signal to the summing junction. The resultant voltage of the quadrant selector
signals will always be an out of phase voltage. The in phase voltage increments
from the ladder switches null out the out of phase resultant and the bias signal mini¬
mizes errors.
The bias signal minimizes errors incurred in the implementation of the cos (0-0)
equation. During those times that the -11.25 degree bit signal is switched in and the
bias signal is absent, a similar bias is provided through the gain of the ladder amplifier.
As the angle 0 becomes greater, the operation described repeats with S12 and
S13 alternating on and off every 11.25 degrees. In the second quadrant, the opera¬
tion continues with switches S9 and S10 alternating on and off. In the third quadrant,
switches S12 and S13 again are operational and in the fourth quadrant, S9 and S10
regain control.
The resolver signals contain a certain percentage of quadrature (reactive) com¬
ponent which, if large enough, could cause the fine schmitt trigger error detector to
fire. To eliminate this possibility, a quadrature reject circuit is incorporated into the
MSA & QR module. The quadrature component is rejected by taking the cos (0-0)
output of the ladder amplifier and phase shifting it 90 degrees to obtain a cos (0- 0)
790° signal which is used as a reference for a phase sensitive demodulator and a
modulator (chopper). The 800 cps output of the main summing amplifier is sampled,
amplified, and applied to the phase sensitive demodulator. If the main summing
amplifier output contains any quadrature component, this value will be demodulated
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
and allowed to charge a capacitor in a filter circuit. If the output of the main sum¬
ming amplifier is an out of phase voltage, the dc charge on the capacitor will be
negative. If the output of the main summing amplifier is an in phase voltage, the
dc charge on the capacitor will be a positive potential.
The dc charge on the capacitor is applied as an input to the chopper which is
keyed by the cos (d-ip) /90° signal. The modulated output from the chopper is 180
degrees out of phase with respect to the quadrature component. The chopper output
is amplified and applied to the main summing junction where it tends to oppose any
quadrature component present at the summing junction. The cos (0-0) /?0° signal
is also sent to the fail detect circuits in the mode module for internal monitoring
purposes.
The main summing amplifier output is applied to an error amplifier. The output
of the error amplifier is applied to two schmitt triggers. One schmitt trigger gen¬
erates an 800 cps square wave output, referred to as the high ternary level signal
F2, which is applied to the read counter logic section of the error counter and
logic module causing the read counter to be incremented at a high rate (12.8 kpps).
The second schmitt trigger generates an 800 cps square wave output, referred to as
the fine ternary level signal Fi, which causes the read counter to be incremented
at a low rate (800 pps). The high level schmitt trigger will fire whenever the error
amplifier output is greater than 4 v peak to peak nominal. When the read counter
is within 20 bits (approximately 0.1 degree) of reading the gimbal angle, the high
level schmitt trigger ceases to fire and the fine schmitt trigger takes over to cause
the read counter to be incremented at the low rate. As long as the error signal is
large enough (two bits or greater from null) to fire the fine schmitt trigger, the
system will not be nulled and incrementing pulses will be sent to the read counter.
The read counter will change the switching configuration to select different values of
0 until 0 is within two bits of equaling 0 . When this match occurs, the output of the
error amplifier will have been reduced to below the 200 millivolt peak to peak nomi¬
nal triggering level of the fine schmitt trigger and the system will be nulled.
The output of the main summing amplifier is referred to as the fine error signal
and is equivalent to sin 16 (6-0). This signal is applied to the fail detect circuits
in the mode module for internal monitoring purposes. The fine error is also ampli¬
fied, buffered, and routed to a test point on the CDU test connector for external moni¬
toring purposes. The fine error signal is also sent to the D/A converter module where
it is used as a gimbal rate limiting signal during the ISS coarse align and turn on modes
of operation.
4-4.4 READ COUNTER MODULE. The read counter module consists of the read
counter and associated buffer units and switch logic.
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MANUAL
The read counter contains 16 identical stages allowing each bit in the counter to be
equivalent to approximately 20 arc-seconds. The output of the first stage, 2°, equiva¬
lent to approximately 40 arc-seconds, is sent to the LGC. The read counter can count
up or down. The accumulation of bits in the counter represents $ (CDU angle) which
the CDU is attempting to match to 0 (desired angle). The content of the read counter
is buffered and used as inputs to the switch logic in the coarse system module, quad¬
rant selector module, and MSA & QR.
4-4.5 ERROR ANGLE COUNTER AND LOGIC MODULE. The error angle counter and
logic module contains the error counter and associated logic, error and rate selection
logic, and read counter control logic.
4-4.5. 1 Error Selection Logic. The error selection logic tests the fine ternary level
(Fi) from the main summing amplifier and the coarse ternary level (Cl) from the
coarse module. At interrogate time, the logic produces a selected error signal (S)
having the same time phase as the selected ternary level signal but inverted. The
coarse ternary level (Ci) has priority and, at interrogation, a high speed clamp signal
is produced. The high speed clamp causes the rate select logic to count the read counter
at high speed (12.8 kpps). The clamp also initiates the inhibit next interrogate logic
which inhibits the interrogation of the coarse ternary level signals at the next inter¬
rogate time. The coarse ternary level remains in control until the error angle
(difference between CDU angle and desired angle) is small enough to allow the fine
system to take over control.
4-4. 5. 2 Inhibit Next Interrogate Logic. The purpose of the inhibit next interrogate
logic is to prevent constant interrogation and thus prevent the system from operating
erratically up and down when coarse and fine ternary levels of opposite phase are
present. The logic provides the error selection logic with a clamp signal at the next
interrogate time. Operation of the logic is dependent upon the coarse ternary level
detection and phase pulses 12 and I3.
4-4. 5. 3 Rate Select Logic. The rate select logic provides the proper input pulses for
operation of the read counter. The logic selects low speed (800 pps) or high speed (12.8
kpps) inputs to the read counter. The high speed clamp from the error selection logic
or high ternary level F2 from the main summing amplifier will initiate the high speed
rate. The low rate is provided by the 800 pps output of the auxiliary clock. Ambiguity
override signal Ao forces the rate select logic into high speed.
4-4. 5. 4 Read Counter Up-Down Logic. The read counter up-down logic tests the phase
of the selected error signal generated in the error selection logic and controls the
direction in which the read counter will count. The selected error signal is compared
with the 800 cps reference signal. A selected error signal in phase with the reference
signal causes the counter to count down while a selected error signal out of phase with
the reference signal cuases the counter to count up. The presence of ambiguity override
signal Ao forces the counter to count down. Read counter pulses and up-down pulses
from up-down logic are ANDed and fed to the LGC. Read counter up-down pulses are
fed to the error counter input sync logic.
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4-4. 5. 5 Error Counter Input Sync Logic. The error counter input sync logic accepts
pulses from the LGC and the read counter up-down logic. To prevent LGC pulses and
read counter pulses from occuring simultaneously, an inhibit function is developed which
allows LGC pulses priority. The inhibit function is sent to the error counter drive logic
where it is further developed and sent to the rate select logic to inhibit pulses to the
read counter. When a pulse is being received from the LGC, the read counter and digita¬
lizing operation is inhibited.
4-4. 5. 6 Error Counter Drive Logic. The error counter drive logic provides pulses to
the error counter and an inhibit to the read counter when LGC pulses are being accepted.
Input pulses to the error counter can originate from the LGC or from the read counter.
When input pulses originate from the read counter, the output from the third stage of
the read counter is used. The LGC pulses and A 2^ pulses are converted to pulses at
04 time for input to the error counter. The change in count direction occurs at 02 time
and counting occurs at 04 time.
4-4. 5. 7 Error Counter Up-Down Logic. The error counter up-down logic controls the
direction in which the error counter will count and determines the phase of the output
of the D/A converter. If the error counter is at zero and the next pulse is an up pulse,
the D/A converter polarity will be set to "+" and the count-up direction set. If pulses
continue, the error counter will continue to count up. When the pulses change to down
pulses, the counter will count down, provided the error counter does not contain zero.
4-4. 5. 8 Error Counter. The error counter has nine identical stages. Its inputs may be
LGC pulses or the output of the third stage (2^) of the read counter. Each pulse sent to
the error counter has aweightof 0.044 degree. The error counter can count up or down
and is controlled by the error counter up-down logic. Error counter inputs 0 2 and 03
are control signals which drive the counter. Bit information is fed through buffer circuits
in the error counter to the D/A converter as switch commands.
4-4.6 DIGITAL MODE MODULE. The digital mode module, consists of a clock pulse
generator, auxiliary clock, 25.6 kpps generator, ambiguity logic, and pulses after in¬
terrogate pulse logic. The digital mode module provides pulse commands which are
used throughout the CDU for synchronization, switching, and strobing.
4-4. 6.1 Clock Pulse Generator. The clock pulse generator generates the phase pulses
required by the CDU. A 51.2 kpps pulse train from the LGC is divided by four. By
ANDing appropriate signals, four 3^. sec, 12.8 kpps pulse trains (01,0 2,0 3, and 04)
of different phases are produced. These signals are used throughout the CDU for strob¬
ing and control.
4-4.6. 2 Auxiliary Clock. The auxiliary clock receives phases 01,0 2, and04 from the
clock pulse generator and generates an 800 pps04 signal. The 800 pps04 signal is
generated by dividing the normal 12. 8 kpps 04 signal by 16. The 01 and 02 signals are
control signals which drive the divider. The 800 pps signal provides a low speed count¬
ing rate for the rate select logic in the error angle counter and logic module.
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MANUAL
4-4. 6. 3 25.6 KPPS Generator. The 25.6 kpps generator produces a 25.6 kpps drive
rate by ANDing two 12.8 kpps pulse trains (02 and 04). This 25.6 kpps drive rate is
applied to the +4 volt power supply for synchronization.
4-4. 6.4 Ambiguity Logic. Ambiguity detect signal Ad from the coarse system module
is ANDed with out-of-phase reference pulse R1 and interrogate pulse I to produce
ambiguity override signal A0. Signal A0 is sent to the rate select logic and read
counter up-down logic in the error angle counter and logic module. The override
signal Aq forces the rate select logic into high speed (12.8 kpps) and the up-down logic
into count-down.
4-4. 6. 5 Pulses After Interrogate Pulse Logic. The pulses after interrogate pulse
logic accepts interrogate pulse I from the interrogate module and phases 0 1 through
0 4 from the clock pulse generator. This logic provides the means of synchronizing
interrogate pulse I and the 51.2 kpps computer clock pulses by generating phase pulses
12 and I3 at 0 2 and 0 3 times respectively, after the occurrence of each interrogate
pulse. These synchronized pulses are used in the CDU for synchronization and control
purposes.
4-4.7 INTERROGATE MODULE. The interrogate module generates a portion of the
timing pulses required for CDU operation, produces 14 vdc power, and has pulse
driver circuitry for data and pulse transmission. The interrogate module provides
the following outputs:
(1) 51.2 kpps pulse train to the digital mode module.
(2) 1,600 pps interrogate pulse train used in the CDU ISS channels.
(3) 800 pps A0 reference signal to the ISS inner, middle, and outer error counter
and logic module and to the digital mode module.
(4) 1,600 pps shaft and trunnion interrogate pulses.
(5) 800 pps /oP reference signal to the LORS error counter and logic module and
the digital mode module.
(6) 14 vdc power.
(7) 25.6 kpps pulse train to 4 vdc power supply module.
4-4.7. 1 14 VDC Power Supply. The interrogate module contains two identical 14 vdc
power supplies. The input power for the power supplies is 28 vdc. The power supply
consists of a single transistor whose bias level is controlled by a zener diode. The
14 volt output is taken from the emitter resistor of the transistor. One 14 vdc power
supply provides 14 vdc to the mode module, the D/A converter module, and the CDU test
connector. The output of the second 14 vdc supply is used entirely within the interrogate
module providing 14 vdc to the pulse driver circuits.
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
4-4. 7. 2 ISS Reference Generator. The ISS reference generator develops an 800 pps
square wave train of zero degree phase for use as a reference by the ISS error counter
and logic modules and by the digital mode module. The signal input is voltage from the
ISS 28 v (rms), 800 cps, 1 percent power supply applied through a 5 to 1 step down
transformer. The positive half cycles are detected and used to drive a transistor. The
output of the transistor is an inverted 800 pps square wave.
4-4. 7. 3 Optics and LORS Reference Generator. The optics and LORS reference generator
provides 0 degree phase and 45 degree phase reference signals of 800 pps. The 0 degree
phase reference signal is supplied to the LORS azimuth and elevation error counter and
logic modules. In the CSM application, this signal is supplied to the optics shaft error
counter and logic module. The 45 degree phase reference signal is not used in the LEM
application; it is used only in the CSM application for the optics trunnion error counter
and logic module. The 0 degree phase reference signal is generated in the same manner
as the ISS 0 degree phase reference signal. The 45 degree phase reference signal also
is obtained in the same manner except that the phase of the 800 cps signal input is first
shifted 45 degrees.
4-4. 7. 4 ISS Interrogate Generator. The ISS interrogate generator provides a 1,600 pps,
3 microsecond pulse width pulse train to the digital mode module and to the inner
gimbal, middle gimbal, and outer gimbal error counter and logic modules.
The input to the ISS interrogate generator is a ISS 28 v (rms), 800 cps voltage
which is applied through a 5 to 1 step down transformer. The 5.6 volt signal phase is
shifted 90 degrees by a resistance, capacitance, and transistor phase shift network. The
phase shifted signal is squared by a diode and used to key a square wave generator. The
symmetrical square wave output of the square wave generator is applied to a differen¬
tiating circuit where the leading edge of the square wave is differentiated and inverted.
The trailing edge of the square wave is differentiated only. In this manner, two signals
are obtained which are then combined to key a transistor output stage that develops the
1,600 pps, 3 microsecond pulse width pulse train output.
4-4.7. 5 Shaft Interrogate Generator. The shaft interrogate generator provides a 1, 600
pps, 3 microsecond pulse width pulse train to the LORS azimuth and elevation error
counter and logic" module and to the digital mode module in the LEM. In the CSM, the
pulse train is supplied to the optics shaft error counter and logic module and to the
digital mode module. The operation of the shaft interrogate generator is the same as
the ISS interrogate generator.
4-4. 7. 6 Trunnion Interrogate Generator. The trunnion interrogate generator is not
used in the LEM.
4-4. 7. 7 AGS Pulse Drivers and Logic Circuits. Seven pulse driver circuits in the in¬
ter rogate-moduIe"lHnsnnriSS~g^ to the AGS. Six pulse driver circuits
transmit ±A0G pulses which represent changes of the inner, middle, and outer gimbal
angles. The seventh pulse driver circuit transmits a CDU zero indication to the AGS.
The gimbal angle pulse driver circuits receive A2^ pulses from the read counter, and
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
up level and down level signals from the error counter and logic module. With the pre¬
sence of A 2° pulses and an up level signal, one transistor pulse driver is actuated and
+A0G pulses, representing increasing gimbal angle, are sent to the AGS. Ifadown level
signal is present, the other pulse driver is activated to send -A0G pulses, representing
decreasing gimbal angle, to the AGS. The ±A0G pulses are transmitted through 2 to 1
buffer transformers.
The CDU-zero pulse driver transmits a CDU-zero indication consisting of a 51.2
kpps pulse train to the AGS. The application and removal of the CDU-zero indication
pulse train provides a zero reference from which the AGS may accumulate the incremental
gimbal angle data and thereby obtain initial attitude conditions from the PGNCS.
A 51. 2 kpps inverted pulse train from the digital mode module is used with the CDU-
zero signal from the mode module to activate a transistor pulse driver circuit. The 51.2
kpps output of the pulse driver is routed to the AGS through a 2 to 1 buffer transformer.
4-4. 7. 8 Buffer Transformer. A 2 to 1 buffer transformer located in the interrogate
module routes the 51.2 kpps pulse train from the LGC to the clock pulse generator in
the digital mode module.
4-4,7, 9 25.6 KPPS Pulse Driver. The25.6kpps pulse driver circuit routes a 25. 6 kpps
pulse train from the digital mode module to the 4 vdc power supply where it is used
for synchronization purposes. The output of the transistor pulse driver is transmitted
through a 2 to 1 buffer transformer.
4-4.8 DIGITAL TO ANALOG CONVERTER. The D/A converter converts digital infor¬
mation from the error counter into a dc analog signal and two ac analog signals. One
ac signal provides attitude error information to the FDAI. The second ac signal is the
coarse align error signal supplied to the gimbal servo amplifiers during the coarse
align mode. The dc signal from the three ISS channels of the CDU is not used in the
LEM but the same dc signal from the two LORS channels of the CDU provides LEM
forward and lateral velocity information to the velocity display meters.
The D/A converter consists of a voltage ladder decoder, a scaling amplifier, a
demodulator, and a mixing amplifier. The conversion of digital information into a dc
analog signal by the D/A converter is accomplished in essentially two steps. The
digital information is first converted into an 800 cycle analog signal by the ladder de¬
coder. The ac signal is then converted to a dc analog signal by a demodulator that
rectifies and filters the ac. Before being applied to the demodulator or being used as a
direct ac output, the ac signal is routed through the scaling amplifier which controls
the gain of the signal. The mixing amplifier combines a feedback signal with the ac
analog signal to produce the coarse align error signal.
The D/A converter also contains pulse driver circuits and buffer transformers
which route the ±£0G pulses from the read counter through the error counter and
logic module to the LGC and route the ±A0C pulses from the LGC to the error counter
and logic module.
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4-4.8. 1 Ladder Decoder. Accumulated data bits in the error counter control the oper¬
ation of transistor switches that apply either an ac ground or 800 cps of proper phase
to the ladder resistors. In this manner, a voltage proportional to the binary configura¬
tion of the switches is developed across the ladder network. For simplicity, the op¬
eration will be explained using the three bit converter shown at the upper left of figure
4-17; however, the theory of operation presented applies to the nine bit converter em¬
ployed by the CDU.
Switches S2, and Sq represent transistor switches which are activated by three
data bits from the error counter. (The switch drive circuitry is not shown.) Switch
S2 is closed by the presence of a bit in the most significant bit position (100) and has a
binary weight of 22. Switch Si is closed by the presence of a bit in the next most
significant bit position (010) and has a binary weight of 21. Switch Sq is closed by the
presence of a bit in the least significant bit position and has a binary weight of 2°.
If the data bits from the error counter are 100, switch S2 is closed and applies the
800 cycle input voltage (Vin) to the ladder. The remaining switches are left in their
normally open position and apply ground. The configuration of the ladder resistors is
as shown in Case 1 (A) of figure 4-17. The solution of the series and parallel groups
of resistances shows the resistance above and below the output point to be 1 (as shown
in the equivalent circuit B). Therefore, the input voltage Vin is divided by 2 and ap¬
plied to the scaling amplifier.
With data bits 010, switch Si is closed and the remaining switches open; the resis¬
tor configuration is as shown in Case 2 (A) of figure 4-17. Combining series and par¬
allel resistances produces the equivalent circuit progression A through D. The voltage
at point a, b is determined first and applied to point b. The simple divider ratio of
resistances above and below the output point is then used to find the output voltage as
shown in the final equivalent circuit D. The output voltage shows that VIN is divided
by 4 and applied to the scaling amplifier.
With data bits 001, switch Sq is closed and the remaining switches open; the resis¬
tor configuration is as shown in Case 3 (A) of figure 4-17. Combining series and
parallel resistances produces the equivalent circuit progression A through E. The
voltage at point ab is found first and applied to point b. In the same manner, the volt¬
age at cd is found and applied to point d. The output voltage is now found from the
divider ratio in the final equivalent circuit E. The output voltage shows that Vin is
divided by 8 and applied to the scaling amplifier.
If a combination of switches is closed at the same time, the output voltage will be
equal to the sum of the voltages found for each switch individually. For example, if
switches S2 and Sq are closed simultaneously (by data bits 101) the output voltage would
be:
VIN Vin 5Vin
2 8 8
4-38
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
SIMPLIFIED 3 BIT CONVERTER
CASE I. SWITCH S2 CLOSED
VIN
VIN
S2
S|
So
22
2'
2°
0
0
1
1/8 Vin
0
1
0
1/4 V |N
0
1
1
3/8 Vin
1
0
0
1/2 V|N
1
0
1
5/8 V|N
1
1
0
3/4 V in
1
1
1
7/8 V|N
CASE 2. SWITCH S, CLOSED
CASE 3. SWITCH S0 CLOSED
Figure 4-17. Simplified 3 Bit Converter and Switch Configurations
4-39
LEM MIIMARY GUIDANCE, NAVIGATION, ANDCONTIOl SYSTEM
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MANUAL
The remaining combinations of switch configurations possible from three data bits is
shown in the truth table on figure 4-17. In each case, the 800 cycle output has an am¬
plitude proportional to the binary configuration of the data bit controlled switches. The
nine bit ladder decoder in the D/A converter provides 2^ or 512 steps from 0 volts to
full output voltage in place of the eight steps provided by the three bit ladder decoder.
In the actual transistor switching circuit (the remainder of the D/A converter dis¬
cussion will refer to circuitry shown on schematic 2010028), the data bit inputs to
switches (DD0, DD1, etc.) are normally at a positive voltage. Therefore, the switch
driver Q3 is on and ground is applied to the base of switch Q14 to keep it off. The ac
ground is applied to the ladder resistor network through Q15 which is forward biased
by the 3.3 volt zener voltage (applied to the emitter) from CR4 and by ground applied
to the base. If 0 volts is applied to DD0, Q3 will turn off and Q14 will turn on applying
2.5 volts rms, 800 cycles from Ti to the ladder. The large positive voltage on the
base of Q15 will turn off Q7 removing ac ground from the ladder. The theory of op¬
eration is the same for the remaining 8 switches.
The D/A converter receives 9 data bits from the error counter as inputs. The
error counter also supplies two polarity control signals (+PdA and -Pda) the D/A
converter. These signals determine if an in phase or an out of phase 800 cycle voltage
will be applied to the ladder. This will, in turn, determine the phasing of the D/A
converter ac output signals and the polarity of the D/A converter dc output signals. If
the +Pda signal (0 volts) is applied to the + D/A polarity input, Q13 turns off and Q12
turns on applying in phase voltage to the ladder. If the -Pda signal (0 volts) is applied
to - D/A polarity input, Q1 turns off and Q2 turns on applying out-of-phase voltage to
the ladder.
4-4. 8. 2 D/A Converter Output Stage. The D/A converter output stage consists of the
demodulator, the scaling amplifier/ and the mixing amplifier. The 800 cycle amplitude
modulated signal from the ladder is applied to the scaling amplifier and demodulator
where the gain is controlled to produce a voltage gradient of 300 millivolts dc per de¬
gree at the output of the D/A converter. In the coarse align mode, the ac voltage from
the scaling amplifier is applied as an input to the mixing amplifier.
The scaling amplifier consists of transistors Q33 and Q34 which, along with the
feed-back network, form an amplifier with an ac gain of approximately 3 to 4. The out¬
put of the scaling amplifier is applied to phase sensitive demodulator through trans¬
former T3. The full-wave rectifiers, which consist of both sections of Q38 and Q39,
are controlled by an 800 cycle reference signal through T4. If the ladder output is in
phase with the reference signal, a positive error voltage will develop at the output of
the rectifier. If the ladder output is 180 degrees out of phase with the 800 cycle ref¬
erence signal, a negative error voltage output is produced. The emitter to emitter
connection of the transistor sections of Q38 and Q39 produces collector to emitter
voltage drops of opposite polarity at each transistor section cancelling the overall
voltage drop across the two sections of the transistor. The rectified ac is filtered and
applied as the D/A converter dc error signal to the LEM velocity display meters. The
scaling amplifier also provides an ac analog signal to the FDAI and to the mixing
4-40
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
amplifier in the coarse align mode. Transistor Q32 provides a means of inhibiting the
output of the D/A converter even though there is an error accumulation in the error
counter. The inhibit action occurs when a positive voltage is applied to the inhibit in¬
put causing Q32 to turn on and to short the input of the scaling amplifier to logic ground.
In the coarse align mode, the gimbals are limited to a maximum rate to prevent
damage to the gyros and to allow the read counter to track the gimbal angle accurately.
The fine error signal, sin 16 (0-^) from the main summing amplifier, is fed back to
rate limit the gimbals. The fine error signal is out of phase with the ladder output and
has an amplitude proportional to the difference between the actual gimbal angle and the
angle registered in the read counter. The fine error feedback signal is summed with
theac output from the scaling amplifier to provide the input to the mixing amplifier. The
output of the mixing amplifier is the coarse align error signal to be applied to the
gimbal servo amplifiers during the coarse align mode.
4-4.9 MODE MODULE. The mode module is utilized as an interface module. The mode
module contains circuits to buffer signals and monitor CDU operation. Direct interface
is made between the mode module and the LGC and with other modules within the CDU.
The mode module provides the following:
a. Buffered moding signals
b. Four timing signals
c. ISS and LORS fail signals
d. 14 vdc power supply output
e. LEM forward and lateral velocity signals
The mode module contains six general types of circuits, each of which will be dis¬
cussed.
4-4.9. 1 Moding Buffer Circuits. The moding buffer circuits receive signals from the
LGC and from the digital mode module. These signals are inverted, amplified or other¬
wise processed into moding signals to be sent to other modules of the CDU.
The signals received from the LGC are five moding discretes. The discretes are
0.0 (±2) vdc, LGC ground, applied through a 2,000 ohm source impedance. The buffer
circuits for four of the discretes are identical. These discretes are the ISS CDU zero,
LORS CDU zero, ISS error counter enable, and the LORS D/A error counter enable. In
each case, the discrete biases a transistor inverter into conduction. The positive dc signal
obtained from the inverter is then sent to the moding sync logic of the digital mode module .
The fifth discrete, the coarse align enable, has a two stage buffer circuit consisting of
an inverter and a relay driver transistor. The inverter has a dual output circuit which
provides two positive dc output voltages upon receipt of the coarse align enable discrete
from the LGC. One output is sent to the moding sync logic in the same manner as the
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
previous four moding signals. The second output of the inverter stage is applied to the
relay driver transistor, causing it to turn on. The relay driver provides a current
path to ground which energizes the coarse align relays located in the PSA.
The signals received from the digital mode module are the ISS CDU zero drive and
LORS CDU zero drive signals. These signals are at positive dc voltage level. The
buffer circuits simply invert the signals and send them to other CDU modules.
4-4. 9. 2 14 VDC Power Supply. The 14 vdc power supply contained in the mode module
is identical to the 14 vdc power supplies described in the interrogator module.
4-4. 9. 3 Phase Buffer Circuits. The phase buffer circuits receive four phase pulse
trains, designated 02 drive, 02 drive, 03 drive, and 04 drive, from the digital mode
module. The buffer circuit for each pulse train is a transistor inverter powered by the
4 vdc power supply. All four inverted signals are sent to the error counter and logic
module. The inverted 0 3 and 02 signals are also sent to the read counter module.
4-4. 9. 4 ISS-CDU Fail Detect Circuit. The ISS-CDU fail detect circuit monitors the
tolerance of critical signals. The fail detect circuits can be considered as three inde¬
pendent failure detect and logic circuits, each monitoring a single type of CDU error.
If an out of tolerance condition is detected by the circuits, a failure signal is applied
to a common output OR circuit.
The first ISS-CDU error detect and logic circuit receives the inner, middle, and
outer coarse error signals from the coarse system module, and the inner, middle, and
outer fine errors from the main summing amplifier. These six signals are applied to
a level detector consisting of six voltage divider networks and a common filter section.
The input signals are attenuated, half-wave rectified, and filtered. The voltage level at
the output of the filter section controls the conduction of an output transistor. If any of
the coarse or fine errors exceed tolerance, the voltage level at the output of the filter
section reaches a level sufficient to bias the output transistor into conduction. The out¬
put transistor in turn supplies a failure indication input to the common output OR circuit.
The second ISS-CDU failure detect circuit monitors the inner, middle, and outer
read counter UP level signals to detect an excessive read counter limit cycle frequency.
When the read counter alternately counts up, then down, the input transistor of the fail¬
ure detect circuit alternately turns on and off. The output of the transistor is differ¬
entiated so that a number of positive and negative pulses, corresponding to the fre¬
quency at which the counter changes direction, are developed. The positive pulses are
detected and applied to a common filter section. By integrating the positive pulses, the
filter section develops an output level proportional to the frequency at which the counter
changes direction. When the frequency exceeds tolerance, the output level of the filter
section is sufficient to bias an output driver transistor into conduction. The driver
transistor, in turn, supplies a failure indication to the common output OR circuit.
The third ISS-CDU failure detect circuit monitors the three cos (0-0) /90° error
signals from the inner, middle, and outer main summing amplifiers and also monitors
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the output of the 14 vdc power supply located in the mode module. Each of the three
cos (0-0) /30° signals is applied to an input transistor which conducts when the applied
signal decreases below tolerance. When any of the three input transistors conduct, they
turn off a fourth transistor which had been preventing the conduction of the output
transistor. The proper state of each of the transistors in the circuit is established by
bias levels derived from the 14 vdc supply. If the 14 vdc input decreases below tol¬
erance, bias levels are changed sufficiently to result in the conduction of the output
transistor. When the output transistor conducts, it supplies a failure indication to the
common output OR circuit.
The output OR circuit accepts inputs from the three failure detect circuits previ¬
ously mentioned. The output transistors of those three circuits must conduct through
the same resistor network so that any of the three will develop a voltage drop across
the resistor network. The voltage drop causes the conduction of the input transistor in
the OR circuit. When this transistor conducts, it supplies an input to a time delay
circuit consisting of a resistance-capacitive network and a zener diode. After ap¬
proximately 7 seconds, the zener diode conducts, supplying proper bias to the output
stage of the circuit which consists of two transistors. When the output transistors
conduct, the circuit provides a positive 28 vdc CDU failure indication to the LGC.
4-4. 9. 5 LORS-CDU Fail Detect Circuit. The LORS-CDU fail detect circuit functions in
exactly the same manner as the ISS-CDU fail detect circuit. The only difference be¬
tween the two circuits is that the LORS-CDU fail detect circuit monitors the 14 vdc
power supply located in the interrogate module and only two each from the cos (0-0),
coarse error, fine error, and limit cycle types of signals.
4-4. 9. 6 Moding Relays. Two sets of two relays are located in the mode module. One
set is used only in the CSM to route signals for Saturn steering control after SIVB
Takeover. The second set of relays are used during thrust vector control mode in the
CSM application and during the display inertial data mode in the LEM. The relays are
energized by the LGC display inertial data discrete acting through a relay driver. The
energized relays route the dc error signals, representing LEM forward and lateral
velocity, from the LORS-CDU D/A converter to the LEM velocity display meters.
4-4.10 4 VDC POWER SUPPLY. The 4 vdc power supply (figure 4-18) supplies 4 vdc
logic power to the digital logic circuits of the CDU. The 4 vdc power supply is a dc to
dc converter type consisting of a pulse amplifier-inverter, a multivibrator-chopper, a
power amplifier, a rectifier and filter circuit, and a difference amplifier and series
regulator circuit.
A 25.6 kpps synchronization pulse input is amplified and inverted and used to syn¬
chronize the multivibrator-chopper, whose natural frequency is 11.5 kcps, at 12.8 kcps.
The multivibrator-chopper drives the primary of a transformer which has 28 vdc ap¬
plied to its center tap. The secondary of the transformer is also center tapped and is
coupled to a push-pull power amplifier. The dc input to the power amplifier is sup¬
plied through a series regulator. The power amplifier drives the primary of a trans¬
former to develop a 12.8 kcps square wave. The output from the transformer secondary
is applied to the rectifier and filter circuit where the 4 vdc output is developed.
4-43
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
voc
tl.l
APRS
1 1784
Figure 4-18. 4 VDC Power Supply, Block Diagram
The 4 vdc output is fed back to a difference amplifier that produces an output error
signal proportional to the difference between the 4 vdc output and a reference voltage
level obtained from a zener diode and resistor voltage divider network. The output of
the difference amplifier controls the operation of the series regulator to increase or
decrease the level of the dc input to the power amplifier as necessary to maintain the
power supply output at 4 volts.
4-5 LEM GUIDANCE COMPUTER
\
This paragraph contains a discussion of the theory of operation of the LGC. Two
levels of theory discussion, functional and detailed, are presented for each element of
the LGC. Machine instructions and programs are also described in sufficient detail
for support of maintenance activities.
4-5.1 PROGRAMS. The current LGC program consists of 17 program sections listed
in table 4-1. (This table also indicates where the program sections are located in
fixed memory.) Since the program is not yet complete, the following descriptions are
limited to the functions of the existing program sections. Before describing the pro¬
gram sections, the terms routine, job, and task must be defined. A routine is a se¬
quence of machine instructions which requires a request from an outside source to set
it into operation. A job is a routine executed according to an assigned priority based
4-44
/l\ Fixed-Fixed memory has an alternate
addressing scheme whereby locations
4000-5777 can be addressed as loca¬
tions 2000-3777 in bank 02, and loca¬
tions 6000-7777 can be addressed as
locations 2000-3777 in bank 03.
/2\ There are 22 additional banks in Fixed
Memory: 10 in Flxed-Switcbable, and
12 in Super Bank. The current
program does not yet use these
banks, therefore, they have been
omitted from this table.
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 4-1. Program Storage Allocations
FIXED
-FIXED
FIXED SWITCHABLE MEMORY
&
MEMORY
/h
Bank 00
Bank 01
Bank 04
Bank 05
Bank 06
Bank 07
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
4000
Interrupt
Lead-Ins
4062
6000
2000
2000
List
Processing
2000
2000
2000
2000
Alarm and
Abort
2004
2000
2000
Integration
Initialization
2244
2000
2000
Controller
and
Meter Routines
2076
2000
IMU
Performance
Test 1
2000
T4RUPT
Program
2103
4063
Inter-Bank
Communication
Interpreter
2005
2177
2245
2077
2104
2217
2200
4130
2220,
Pinball
4131
Executive
4303
Executive
Inflight
Alignment
LEM Flight
Control
System Test
KEYRUPT
UPRUPT
4304
Routines
2233
Waitlist
4336
2444
2234
4337
2561
12445
2547
T4RUPT
Program
4374
2562
Waitlist
2766
; 2550
4375
Pinball
Pinball
Pinball
Instruction
Check
Instruction
Check
Orbital
2730
List
list
2767
4707
Processing
Interpreter
Processing
Interpreter
llliSlii
Integration
Program
2731
4710
Alarm and
Abort
4764
Freeh Start
and Restart
RTBOp
Codes
4765
3024
13025 . .
Instruction
Check
3157
3160
5121
3170
3274
5122
3476
: 31 7 1
3275
3461
3515
3477
3462j:::;i
3516
7666
3656
7667
:3657:i:;:;!
5777
:??77’i|;:|!:|iiiijijj!i|
37.7.7.: . :
3777
[3777
3777
3777
: 37 7 7
37.77 MtMM-
37 7?
: 37 7 V';.''' -• T,
4-45/4-46
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
on the relative importance of the job to the overall accomplishment of the mission.
Each job is assigned to a job area which is a group of locations in erasable memory
into which information relating to the job can be stored. A task is a routine executed
at an assigned future time counting ahead from the present time. The following para¬
graphs contain a brief description of the program sections.
4-5. 1.1 Executive. The executive supervises the execution of all requested jobs ac¬
cording to an assigned priority scheme. The job having the highest priority is allowed
to operate until displaced by another job of higher priority. When the job having the
highest priority is completed, the executive initiates the execution of that job having the
next highest priority. If no job is awaiting execution, a dummy job is executed which
keeps the LGC idling until the next job request.
In addition, the executive places jobs into a dormant state when they require the
occurrence of certain external events before proceeding. The executive then must re¬
activate these jobs when the external events have been completed.
4-5. 1.2 Waitlist. Program section waitlist schedules the execution of tasks which
must be executed at a specific time. Waitlist derives its timing from the TIME 3
counter; whenever this counter overflows, program control is transferred to that task
which must be executed next. Waitlist maintains a list of tasks to be performed and,
if the list is not full, dummy tasks are used to fill it. A dummy task performs the
same function for waitlist as the dummy job performs for the executive.
4-5. 1.3 Interpreter. The interpreter translates into basic machine language and ex¬
ecutes that part of the program written in interpretive language. This translation
allows complex operations to be prepared in a compact form at the sacrifice of LGC
operational speed. Routines written in interpretive language contain explicit double
precision, vector, and matrix operations.
4-5. 1.4 RTB Op Codes. The RTB Op (return to basic operation) codes increase the
effectiveness of the interpreter. The RTB Op codes provide a convenient link between
basic and interpretive language and make possible the execution of subroutines in basic
language while operating in the interpretive mode.
4-5. 1.5 Fresh Start and Restart. A fresh start initiates most program sections in re¬
sponse to a keyboard entry from the DSKY. when the LGC is turned on, or when a
serious error condition exists. A restart initiates most program sections after a GO
sequence and returns program control to the beginning of the operation which was
interrupted by the error.
4-5. 1.6 Interrupt Lead-In Routines. The interrupt lead-in routines save the contents
of register A (accumulator) and transfer program control to the routines that must be
executed when an interrupt transfer request is recognized. The interrupt transfer
routines transfer program control to routines T6RUPT, T5RUPT, T3RUPT, T4RUPT,
KEYRUPT, UPRUPT, DOWNRUPT, RADRUPT, and HNDRUPT.
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LEM PRIMARY 6UIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
4-5. 1.7 T4RUPT. Program section T4RUPT is activated when the TIME 4 counter
overflows, and serves as a connection between the program and devices external to the
LGC.
4-5. 1.8 KEYRUPT and UPRUPT Processor. Program section KEYRUPT and UPRUPT
processor accepts data from the t)SkY, LORS, and uplink (unmanned flights). A
KEYRUPT is initiated each time a DSKY key is pressed or when a specific discrete is
received from LORS. An UPRUPT is initiated whenever data is received via uplink.
After the data has been accepted, KEYRUPT and UPRUPT processor requests the
execution of program section pinball which processes the data.
4-5. 1.9 Interbank Communication. Interbank communication allows the transfer of
information and/or control between banks in the fixed- switchable portion of fixed
memory. This transfer is accomplished by transferring program control to fixed-
fixed memory where the bank address can conveniently be changed. Then, register S
is set to address the desired location within the proper bank. Program control is then
transferred to the correct location in fixed-switchable memory.
4-5.1.10 Pinball. Program section pinball processes information exchanged between
the LGC and the astronaut. These exchanges are initiated primarily by keycode ac¬
tion; however, exchanges can also be initiated under internal program control. Various
functions are performed in response to requests from the keyboard; information re¬
sulting from these keyboard requests or internal requests from other program sec¬
tions is displayed on the DSKY.
4-5.1.11 Alarm and Abort. Program section alarm and abort causes the display of
certain failure messages on the DSKY. These failures are defined as either an alarm
or an abort. Except for repeated alarms, an alarm is a failure which does not re¬
quire a fresh start or restart. In the case of repeated alarms, the astronaut may initi¬
ate a manual fresh start via a keyboard entry. An abort is a failure which requires
fresh start. Both failure conditions are displayed on the DSKY in a five character
code of the form AAANN where AAA identifies the program section or routine in which
the failure occurred and NN identifies the specific error which has occurred.
4-5.1.12 Controller and Meter Routines. The controller and meter routines service
the hand controller inputs following a hand controller interrupt.
4-5.1.13 Orbital Integration. Orbital integration computes position and velocity of the
spacecraft during coasting periods of the mission. Position and velocity are maintained
in the LGC in non- rotating rectangular coordinates and referenced to the earth.
4-5.1.14 In-Flight Alignment. Program section in-flight alignment provides the frame¬
work for aligning the IMU. The program section consists of a set of routines written
in interpretive language which are used for geometric transformation of the many
coordinate axes needed in the in-flight alignment process.
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LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
4-5.1.15 Instruction Check. This program section exercises most of the control
pulses in the LGC to check its performance. This is accomplished by initiating vari¬
ous program instructions. Most of the control pulses in an instruction are used every
time that particular instruction is executed; however, the functions that some of these
pulses perform are not utilized until some time later. Therefore, a systematic
method is used to exercise those pulses not used immediately.
4-5.1.16 Flight Control System Test. This program section is used to execute five
chains of tasks to test the LEM Flight Control System (FCS). These tests include
turning various LEM engines on and off, issuing various engine control commands,
and monitoring the LEM FCS input channels.
4-5.2 MACHINE INSTRUCTIONS. The LGC has three classes of machine instructions:
regular, involuntary, and peripheral. Regular instructions can be written into a pro¬
gram and are executed in whatever sequence they have been stored in memory. Regular
instructions are subdivided into basic, extracode, channel, and special instructions.
Involuntary instructions are not programmable, with the exception of one instruction
which may be programmed to test LGC operations. Involuntary instructions have pri¬
ority over regular instructions and are executed at the occurrence of certain events
during normal LGC operation. Involuntary instructions are subdivided into interrupt
and counter instructions. The peripheral instructions are used when the LGC is con¬
nected to the computer test set (CTS) or other applicable peripheral equipment. Dur¬
ing the execution of any peripheral instruction, the LGC is in the monitor stop mode
and cannot execute any regular or involuntary instructions.
4-5. 2.1 Regular Instructions. The difference between the four types of regular instruc¬
tions is directly related to the way in which the LGC interprets an instruction word.
Instruction words stored in memory are called basic instruction words. As shown in
figure 4-19, these words contain a three bit order code field and a twelve bit address
field. The content of the order code field defines the instruction and is represented by
a single digit octal number with the octal point at the right. The content of the address
field defines a location and is represented by a four digit octal number with the octal
point at the left. An instruction word in memory therefore maybe written as a five digit
octal number, e.g. 2.0314. The order code field is extended an additional bit when the
basic instruction is transferred from memory to the central processor. Therefore, the
instruction word used in the example changes to 02.0314 in the central processor. This
additional high order bit is always logic ZERO for basic instructions. When the LGC is
switched to the extend mode, the high order bit is logic ONE indicating an extra code or
channel instruction will be executed next.
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OCTAL
POINT
4
h - OROnELO°OE - "i* - ADDRESS FIELD
o BASIC INSTRUCTION WORD IN MEMORY
OCTAL
POINT
ORDER CODE
FIELD
ADORESS FIELD
NOTE: BITS 16 ANO 15 ARE ALWAYS EQUAL
b BASIC INSTRUCTION WORD IN CENTRAL PROCESSOR
OCTAL
POINT
? ?
2
r 'i r \r \
EXT
16
14
1 3
12
II
10
c FXTENDED ORDER CODE FIELD
40700
Figure 4-19. Basic Instruction Word Format
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The LGC logic permits the use of the three high order bits (one octal digit) of the
address field to further lengthen the order code field. A typical instruction can then be
represented as 02.0 numerically. This encroachment on the address field limits the
use of some instructions to a certain portion of memory. The high order bits of the
address field may be used this way because of the differences between fixed and eras¬
able memory. The instructions which apply only to erasable memory do not copy the
two high order bits of the address field into the address register. However, the address
register receives the entire address field for those instructions which apply to fixed
memory.
The special instructions are address-dependent basic instructions and the order
codes are represented as 00.0006 numerically. Those address-dependent instructions
which may be combined with any order code are represented, for example, as .0021
which is the entire content of the address field.
4-5. 2. 2 Involuntary Instructions. Involuntary instructions consist of interrupt and
counter instructions. The interrupt instructions are not programmable although they
have order codes. The order codes are established by LGC logic and the inter¬
rupt instructions are executed on a priority basis. Counter instructions are also in¬
terrupt instructions in the sense that they delay the program for a short time. Counter
instructions do not have operation codes and are executed involuntarily when the LGC
is accepting incremental inputs or is providing incremental pulse rate outputs.
4-5. 2. 3 Peripheral Instructions. Peripheral instructions consist of keyboard and tape
instructions. These instructions are initiated by an operator using the peripheral
equipment. One peripheral instruction has an order code which is established by
LGC logic. The others do not have order codes and are executed involuntarily like
counter instructions.
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4-5. 2. 4 Functional Description. Machine instructions can be divided by function into eight
categories. Each category of instructions performs similar operations. For example,
the add, subtract, multiply, and divide instructions perform arithmetic operations. The
eight functional categories of machine instructions are:
(1) Sequence changing
(2) Fetching and storing
(3) Modifying
(4) Arithmetic and logic
(5) Input- output
(6) Editing
(7) Priority
(8) Peripheral
Table 4-II lists the eight functional categories of machine instructions. Also listed in
table 4-n are subfunctional grouping, names, and mnemonic instruction words for each
instruction. The instruction word addresses are represented by the following letters:
(1) K for any address
(2) CP for central processor addresses
(3) E for erasable memory addresses
(4) F for fixed memory addresses
(5) C for counter address
(6) H for channel addresses
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Table 4-n. Functional Organization of Machine Instructions
Type
Instruction
SEQUENCE CHANGING
Transfer control
TC K
Transfer control
TCF F
Transfer control to fixed memory
Decision making
CCS E
Count, compare, and skip
BZF F
Branch on zero to fixed memory
BZMF F
Branch on zero or minus to fixed
memory
FETCHING AND STORING
Copying
CA K
Clear and add
CS K
Clear and subtract
DCA K
Double precision clear and add
DCS K
Double precision clear and subtract
Storing
TS E
Transfer to storage
Exchange
XCH E
Exchange A
QXCH E
Exchange Q
LXCH E
Exchange L
DXCH E
Double exchange
MODIFYING
Indexing
NDX E
Index basic
NDX K
Index extracode
ARITHMETIC AND LOGIC
Arithmetic
AD K
Add
SU E
Subtract
MP K
Multiply
DV E
Divide
Adding and storing
ADS E
Add and store
DAS E
Double precision add and store
(Sheet 1 of 3)
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Table 4— II. Functional Organization of Machine Instructions
Type
Instruction
ARITHMETIC AND LOGIC (cont)
Incrementing
INCR E
Increment
AUG E
Augment
DIM E
Diminish
Angular subtraction
MSU E
Modular subtract
Logic
MSK K
Mask or AND
INPUT-
•OUTPUT
Read
READ H
Read channel
RAND H
Read and AND
ROR H
Read and OR
RXOR H
Read and EXCLUSIVE OR
Write
WRITE H
Write channel
WAND H
Write and AND
WOR H
Write and OR
EDITING
Control
RE LINT
Release interrupt inhibit
INHINT
Inhibit interrupt
EXTEND
Extend order code field
RESUME
Resume interrupted program
Shift and cycle
CYR
Cycle right
SR
Shift right
CYL
Cycle left
EDOP
Edit operator
(Sheet 2 of 3)
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Table 4- II. Functional Organization of Machine Instructions
Type
Instruction
PRIORITY
Interrupt
RUPT F
Interrupt
GOJ F
Start
Counter
PINC C
Plus increment
MINC C
Minus increment or decrement
DINC C
Diminish increment
PCDU C
Increment CDU
MCDU C
Decrement CDU
SHINC C
Shift increment
SHANC C
Shift add increment
PERIPHERAL
Transfer control
TCSAJ K
Transfer control to specified
address
Read
FETCH K
Read memory
INOTRD H
Read channel
Load
STORE E
Load memory
INOTLD H
Load channel
(Sheet 3 of 3)
4-5. 2. 4. 1 Sequence Changing Instructions. Two categories of sequence changing in¬
structions are:
(1) Transfer control instructions - TC K, TCF F
(2) Decision instructions - CCS E, BZF F, BZMF F
The program control instructions determine the path that the program follows. In¬
struction TC K takes the next instruction from the location designated by the program¬
mer instead of the next higher location. Instruction TCF F can only take instructions
from designated fixed memory locations.
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The decision instructions branch to alternate program paths in response to pre¬
cisely defined conditions. Instruction CCS E tests for positive non-zero, plus zero,
negative non-zero, and minus zero quantities and branches to one of four corresponding
program paths. Instruction BZF F transfers control on a plus zero quantity to an alter¬
nate program path in fixed memory. The program follows its normal path if the quantity
being tested is not plus zero. Similarly, instruction BZM F branches to an alternate
path in fixed memory if the quantity under test is plus zero or negative.
4-5. 2. 4. 2 Fetching and Storing Instructions. Three categories of the fetch and store
instructions are:
(1) Copying instructions - CA K, CS K, DCA K, DCS K
(2) Storing instruction - TS E
(3) Exchange instruction - XCH E, LXCH E, DXCH E, QXCH E
The copy instructions are used for duplicating data in another register. The content
of any location may be copied into the single or double precision accumulators with in¬
structions CA K and DCA K, respectively. The content of any location may be comple¬
mented and then copied into the accumulators with instructions CS K and DCS K. The
content of the single precision accumulator may be copied into any erasable memory
location with instruction TS E.
The content of registers A, L, or Q may be exchanged with that of any erasable
memory location using instructions XCH E, LXCH E, or QXCH E, respectively. The
content of the double precision accumulator may be exchanged with that in designated
erasable memory locations using instruction DXCH E.
4-5. 2. 4. 3 Modifying Instructions . The modifying instructions are NDX E (basic) and
NDX K (extracode). Both instructions derive the next instruction to be executed.
4-5. 2. 4. 4 Arithmetic and Logic Instructions. Five categories of the arithmetic and
logic instructions are:
(1) Basic arithmetic instructions - AD K, SU E, MP K, DV E
(2) Add and store instructions - ADS E, DAS E
(3) Angular subtract instructions - MSU E
(4) Incrementing instructions - INCR E, AUG E, DIM E
(5) Boolean AND instructions - MSK K
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The basic arithmetic operations, addition, subtraction, multiplication, and division
in the ONE'S complement binary number system are performed with instructions AD K,
SU E, MP K, and DV E, respectively. These instructions employ the conventional rules
of algebra treating operators, operands, and resultants as signed (positive or negative)
quantities. The operands and resultants are contained in the double precision accumu¬
lator (registers A and L) and the operators are obtained from any erasable memory
location designated by the programmer.
Addition may also be performed with instruction ADS E which stores the resultant
in register A and erasable memory. Instruction DAS E is used for double precision
addition and storage. The difference between any TWO's complement numbers repre¬
senting angular or periodic data may be obtained with instruction MSU E. The difference
is a ONE’S complement number stored in the designated erasable memory location.
The content of any erasable memory location designated by the programmer may
be incremented by one with instruction INCR E. Instruction AUG E will increment the
absolute value by one, whereas instruction DIM E will decrement the absolute value by
one. If the designated address is OO260, 0027a, or 00308 and overflow occurs, program
control is automatically transferred to a reserved fixed memory location. If the address
is 0025 8 and overflow occurs, the T2 time counter is automatically incremented by a
counter instruction.
The MSK K instruction follows the basic rules of Boolean algebra and performs
the AND operation. The operands and resultants are stored in the accumulator and
the operator are obtained from any location designated by the programmer.
4-5. 2.4. 5 Input-Output Instructions. The two categories of input-output or channel in¬
structions are:
(1) Read instructions - READ H, RAND H, ROR H, RXOR H
(2) Write instructions - WRITE H, WAND H, WOR H
Instructions READ H and WRITE H copy the content at the channel location into
register A and the content of A into the channel location, respectively.
The logic instructions follow the basic rules of Boolean algebra, performing AND,
OR, and EXCLUSIVE OR operations. The operands and resultants are stored in the ac¬
cumulator and the operators are obtained from the location designated by the pro¬
grammer.
Instructions RAND H and WAND H also perform the AND operation but the operator
must be selected from a channel location. Instruction WAND H stores the resultant
in both register A and the designated channel location. Instructions ROR H and WOR H
perform the OR operation and RXOR H performs the EXCLUSIVE OR operation with
the operator of any channel location. Instruction WOR H stores the resultant in both
register A and the designated location. It is important to remember that registers
L and Q are channel locations as well as addressable CP locations.
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4-5. 2.4. 6 Editing Instructions. The editing instructions are address dependent in¬
structions and are contained in two categories:
(1) Control instructions - RESUME, EXTEND, INHINT, RELINT
(2) Shift and cycle instructions - CYR, SR, CYL, EDOP
Instruction RESUME returns to the program that was being executed when an in¬
terrupt occurred. Instruction EXTEND sets the high order bit of the operation code.
Instructions INHINT and RELINT respectively inhibit and permit interrupts.
4. 5. 2. 4. 7 Priority Instructions. The two categories of priority instructions are:
(1) Interrupting instructions - RUPT F, GOJ F
(2) Counter instructions - PINC C, MINC C, PCDU C, MCDU C, DINC C, SHINC C,
SHANC C
Instructions RUPT F and GOJ F transfer control to fixed memory. The counter in¬
structions are not programmable and apply to those erasable memory locations listed
in table 4- III. Instructions PINC C and MINC C increment and decrement, respectively,
the contents of the addressed counter. Instructions PCDU C and MCDU C increment
and decrement, respectively, the CDU counters. The CDU counters always contain
TWO's complement numbers. Instruction DINC C controls the output rate pulses. In¬
structions SHINC C and SHANC C perform serial-to-parallel conversion.
4. 5. 2.4. 8 Peripheral Instructions. Three groups of peripheral instructions are:
(1) Read - FETCH K, INOTRD II
(2) Load - STORE E, INOTLD H
(3) Transfer control - TCSAJ K
The peripheral instructions apply only when the LGC is connected to the CTS or the
program analyzer console (PAC). Instructions FETCH K and INOTRD H are used for
monitoring the content of memory and channel locations, respectively. Instructions
STORE E and INOTLD H are used for loading erasable memory and channel locations
respectively with data supplied by the peripheral equipment. Instruction TCSAJ K is
used for initiating the instruction at any location.
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Table 4- in. Counter Instructions
Location
Counter
Instruction
0024
T2
PINC
0025
T4
PINC
0026
T3
PINC
0027
T4
PINC
0030
T5
PINC
0031
T6
DINC
0032
CDUX
PCDU, MCDU
0033
CDUY
PCDU, MCDU
0034
CDUZ
PCDU, MCDU
0035
TRN
PCDU, MCDU
0036
SHAFT
PCDU, MCDU
0037
PIPX
PINC, MINC
0040
PIPY
PINC, MINC
0041
PIPZ
PINC, MINC
0042
BMAGX
PINC, MINC
0043
BMAGY
PINC, MINC
0044
BMAGZ
PINC, MINC
0045
INLINK
SHANC, SHINC
0046
RNRAD
SHANC, SHINC
0047
GYRO
DINC
0050
CDUX
DINC
0051
CDUY
DINC
0052
CDUZ
DINC
0053
TRUN
DINC
0054
SHAFT
DINC
0055
THRST
DINC
0056
EMS
DINC
0057
OTLNK
SHINC
0060
ALT
SHINC
4-5. 2.4. 9 Alphabetical Listing. Table 4-IV is an alphabetical listing of machine in¬
structions. This table includes the order code, description, and execution time of each
instruction. The symbol c(A), c(L), and so forth mean the content of A or the content
of L. The letters K, E, H, F, and C refer to memory locations. The execution time
is given in memory cycle times (MCT). One MCT equals approximately twelve micro¬
seconds.
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Table 4-IV. Machine Instructions, Alphabetical Listing
Symbolic
Instruction
Word
Order Code
c(SQ)
Description
Execution
Time in
MCT’s
AD K
06.
Basic instruction; adds c(K) to c(A);
stores result in A; takes next instruction
from 1+1 where I is location of AD K.
2
ADS E
02.6
Basic instruction; adds c(A) to c(E) and
stores result in both A and E; takes next
instruction from 1+1 where I is location of
ADS E.
2
AUG E
12.4
Extracode instruction; adds +1 to | c(E) | ,
i.e. , adds +1 if c(E) is positive and -1 if
c(E) is negative; stores result in E; takes
next instruction from 1+1 where I is loca¬
tion of AUG E.
2
BZF F
11.2
Extracode instruction; takes next instruc-
1 if c(A)
11.4
tion from F if c(A) is +0; otherwise takes
is +0;
11.6
next instruction from 1+1 where I is loca¬
tion of BZF F.
otherwise
2
BZMF F
16.2
Extracode instruction; takes next instruc-
1 if c(A)
16.4
tion from F if c(A) is +0 or negative;
is +0 or
16.6
otherwise takes next instruction from 1+1
where I is location of BZMF F.
negative;
otherwise
2
CA K
03.
Basic instruction; copies c(K) into A; takes
next instruction from 1+1 where I is loca¬
tion of CA K.
2
CCS E
01.0
Basic instruction; if c(E) is non-zero and
positive, takes next instruction from 1+1
where I is location of CCS E. Also, adds
-1 to c(E) and stores result in A. If c(E) is
+0, takes next instruction from 1+2 and sets
c(A) to +0. If c(E) is non-zero and negative,
takes next instruction from 1+3, adds -1 to
c(E), and stores result in A. If c(E) is -0,
takes next instruction from 1+4 and sets
c(A) to +0.
2
(Sheet 1 of 8)
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Table 4-IV. Machine Instructions, Alphabetical Listing
Symbolic
Instruction
Word
Order Code
c(SQ)
Description
Execution
Time in
MCT's
CS K
04.
Basic instruction; copies c(K) into A; takes
next instruction from 1+1 where I is loca¬
tion of CS K.
2
CY L
.0022
Special instruction; cycles quantity, which
is entered into location 0022, one place to
left.
2 or 3
CYR
.0020
Special instruction; cycles quantity, which
is entered into location 0020, one place to
right.
2 or 3
DAS E
02.0
Basic instruction; adds c(A, L) to c(E,
E+l); stores result in E and E+l; sets
c(L) to +0 and sets c(A) to net overflow if
address E is not 0000 e. Net overflow is +1
for positive overflow, -1 for negative over¬
flow, otherwise c(A) is set to +0. Takes
next instruction from 1+1 where I is loca¬
tion of DAS E.
3
DCA K
13.
Extracode instruction; copies c(K, K+l)
into A and L; takes next instruction from
1+1 where I is location of DCA K.
3
DCS K
14.
Extracode instruction; copies c(K, K+l)
into A and L; takes next instruction from
1+1 where I is location of DCS K.
3
DIM E
12.6
Extracode instruction; adds -1 to | c(E)| ,
i.e. , adds -1 if c(E) is non-zero and posi¬
tive and +1 if c(E) is non-zero and negative;
stores result in E; takes next instruction
from 1+1 where I is location of DIM E.
2
(Sheet 2 of 8)
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Table 4-IV. Machine Instructions, Alphabetical Listing
Symbolic
Instruction
Word
Order Code
c(SQ)
Description
Execution
Time in
MCT’s
DINC C
None
Counter instruction; adds +1 to c(C) if
c(C) is negative and provides negative rate
output pulses; adds -1 to c(C) if c(C) is
positive and provides positive rate output
pulses; provides no rate output pulses
when c(C) is ± 0; stores result in C; de¬
lays program execution for 1 MCT.
1
DV E
11.0
Extracode instruction; divides c(A, L) by
c(E); stores quotient in A; stores re¬
mainder in L; takes next instruction from
1+1 where I is location of DV E.
6
DXCH E
05.2
Basic instruction; exchanges c(E, E+l) with
c(A, L); takes next instruction from 1+1
where I is location of DXCH E.
3
EDOP
.0023
Special instruction; shifts quantity, which
is entered into location 0023, seven
places to left.
2 or 3
00.
Interrupting instruction; transfers control
to instruction stored in location 4000 6.
2
EXTEND
00.0006
Special instruction; see TC K.
1
FETCH K
None
Peripheral instruction; reads and dis¬
plays c(K) as binary numbers on CTS,
where K is address supplied by CTS.
2
INCR E
02.4
Basic instruction; adds +1 to c(E); stores
result in E; takes instruction from 1+1
where I is location of INCR E.
2
INHINT
00.0003
Special instruction; see TC K.
1
(Sheet 3 of 8)
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Table 4-IV. Machine Instructions, Alphabetical Listing
Symbolic
Instruction
Word
Order Code
c(SQ)
Description
Execution
Time in
MCT's
INOTLD H
None
Peripheral instruction; loads data supplied
by CTS into location H, where H is channel
address also supplied by CTS.
1
INOTRD H
None
Peripheral instruction; reads and displays
c(H) as binary number on CTS, where H
is channel address supplied by CTS.
1
LXCH E
02.2
Basic instruction; exchanges c(E) with
c(L); takes next instruction from 1+1
where I is location of LXCH E.
2
MCDU C
None
Counter instruction; adds -1 (two’s com¬
plement) to c(C); delays program execu¬
tion for 1 MCT.
1
MINC C
None
Counter instruction; adds -1 to c(C);
delays program execution for 1 MCT.
1
MP K
17.
Extracode instruction; multiplies c(A)
by c(E); stores result in A and L; c(A,
L) agree in sign; takes next instruction
from 1+1 where I is location of MP E.
3
MSK K
07.
Basic instruction; AND's c(A) with c(K);
stores result in A; takes next instruction
from 1+1 where I is location of MSK K.
2
MSU E
12.0
Extracode instruction; forms the signed
one’s complement difference between
c(A) and c(E) where c(A) and c(E) are un¬
signed (modular or periodic) two’s comple¬
ment numbers; stores result in A; takes
next instruction from 1+1 where I is loca¬
tion of MSU E.
2
(Sheet 4 of 8)
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Table 4-IV. Machine Instructions, Alphabetical Listing
Symbolic
Instruction
Word
Order Code
c(SQ)
Description
Execution
Time in
MCT's
NDX E
05.0
Basic instruction; adds c(K) to c(I+l) where
I is location of NDX E; takes sum of c(K)
+ c(I+l) as next instruction.
2
NDX K
15.
Extracode instruction; adds c(K) to c(I+l)
where I is location of NDX K; sets extra
code switch; sum of c(K) + c(I+l) becomes
an extracode instruction which is taken
as next instruction.
2
PCDU C
None
Counter instruction; adds +1 (two's comple¬
ment) to c(C); delays program execution
for 1 MCT.
1
PINC C
None
Counter instruction; adds +1 to c(C); de¬
lays program execution for 1 MCT.
1
QXCH E
12.2
Extracode instruction; exchanges c(E)
with c(L); takes next instruction from
1+1 where I is location of QXCH E.
2
RAND H
10.2
Channel instruction; AND's c(H) with
c(A); stores result in A; takes next in¬
struction from 1+1 where I is location of
RAND H.
2
READ H
10.0
Channel instruction; copies c(H) into A;
takes next instruction from 1+1 where I
is location of READ H.
2
ROR H
10.4
Channel instruction; OR's c(H) with c(A);
stores result in A; takes next instruction
from 1+1 where I is location of ROR H.
2
RE LINT
00.0003
Special instruction; see TC K.
1
RESUME
05.0017
Special instruction; takes next instruction
from return address.
1
(Sheet 5 of 8)
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Table 4-IV. Machine Instructions, Alphabetical Listing
Symbolic
Instruction
Word
Order Code
c(SQ)
Description
Execution
Time in
MCT’s
RUPT F
10.7
Interrupting instruction; takes next in¬
struction from location F; stores c(B)
(instruction that was to be executed) in
location 00178 ; stores c(Z) = I in location
0015a , where I is assigned location of
instruction stored in 00178.
3
RXOR H
10.6
Channel instruction; forms the exclusive
OR of c(H) and c(A); stores result in A;
takes next instruction from 1+1 where I
is location of RXOR H.
2
SHANC C
None
Counter instruction; doubles c(C) and adds
+1; stores result in C; delays program
execution for 1 MCT.
1
SfflNC C
None
Counter instruction; doubles c(C); stores
result in C; delays program execution
for 1 MCT.
1
SR
.0021
Special instruction; shifts quantity, which
is entered into location 0021, one place
to right.
2 or 3
STORE E
None
Peripheral instruction; data supplied by
CTS is stored in location E where E is
address supplied by CTS; delays program
execution for 2 MCT’s.
2
SU E
16.0
Extracode instruction; subtracts c(A) from
c(E); stores result in A; takes next instruc¬
tion from 1+1 where I is location of SU E.
2
(Sheet 6 of 8)
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Table 4 -IV.
Machine Instructions, Alphabetical Listing
Symbolic
Instruction
Word
Order Code
c(SQ)
Description
Execution
Time in
MCT’s
TC K
00.
Basic instruction; takes next instruction
from K; stores 1+1 in Q where I is loca¬
tion of TC K; if K is 0006 8 (EXTEND),
sets extracode switch and takes next in¬
struction from 1+1; if K is 0004 8 (INHINT)
sets inhibit interrupt switch and takes
next instruction from 1+1; if K is 0003®
(RE LINT), resets inhibit interrupt switch
and takes next instruction from 1+1.
1
TCF F
01.2
01.4
01.6
Basic instruction; takes next instruction
from F.
1
TCSAJ K
Peripheral instruction; takes next in¬
struction from K where K is address
supplied by CTS.
2
TS E
05.4
Basic instruction; if c(A) is not an over¬
flow quantity, copies c(A) into K and takes
next instruction from 1+1 where I is loca¬
tion of TS K; if c(A) is a positive overflow
quantity, copies c(A) into K, sets c(A) to
+1, and takes next instruction from 1+2;
if c(A) is a negative overflow quantity,
copies c(A) into K, sets c(A) to -1, and
takes next instruction from 1+1.
2
WAND H
10.3
Channel instruction; AND’s c(H) with c(A);
stores result in H and A; takes next in¬
struction from 1+1 where I is location of
WAND H.
2
WOR H
10.5
Channel instruction; OR's c(H) with c(A);
stores result in H and A; takes next in¬
struction from 1+1 where I is location of
WOR H.
2
(Sheet 7 of 8)
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MANUAL
Table 4- IV. Machine Instructions, Alphabetical Listing
Symbolic
Order Code
Description
Execution
Instruction
c(SQ)
Time in
Word
MCT’s
WRITE H
10.1
Channel instruction; copies c(A) into H;
takes next instruction from 1+1 where I is
2
location of WRITE H.
XCH E
05.6
Basic instruction; exchanges c(A) with c(E);
takes next instruction from 1+1 where I is
2
location of XCH E.
(Sheet 8 of 8)
4-5.2. 5 Subinstruction Commands and Control Pulses. The basic elements which com¬
prise machine instructions are control pulses and subinstruction commands. Control
pulses are sequence generator signals which regulate data flow within the LGC. Machine
instructions use a large variety of control pulses to accomplish various functions.
The data must be regulated in an orderly sequence and certain information must not
be destroyed during the execution of an instruction. In addition, the machine in¬
struction must be executed within the memory cycle timing framework which consists
of twelve one-microsecond periods. Some instructions are so involved that two or
more memory cycle times are required to accomplish a task. Each memory cycle
time is controlled by a subinstruction command, regardless of the number of MCT’s
required to do a job. Instruction TC K for example takes one MCT to be executed and
is controlled by subinstruction command TCO. Table 4-V lists all of the machine in¬
structions by order code. The associated subinstructions are also listed. Some in¬
structions use common subinstructions like STD2. Table 4-V also lists the content
of the stage counter for each subinstruction. The number after each subinstruction
like DAS1 reflects the count of the stage counter.
Information is transferred from one register to another by read, clear, and
write control pulses. The clear pulses are generated automatically when a write
pulse is generated to clear a register before data is written into it. The control
pulses RZ and WS, for instance, occurring simultaneously, duplicate (copy) the con¬
tent of register Z in register S. There are five types of control pulses: read, write,
test, direct exchange, and special purpose control pulses, discussed in the following
paragraphs.
4-5. 2. 5.1 Read Control Pulses. A read control pulse places on the write lines data
which is to be transferred (copied) into a register. Most read control pulses such as
RA, RB, and RZ read the content of a specific register onto the write lines. Control
4-67
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Table 4-V. Subinstructions
Order
Code
c(SQ)
Mnemonic
Operation
Code
Mnemonic
Subinstruction
Code
Register
SQ
Display
Stage
Counter
Display
RE(
1ULAR INSTRUCTIONS
00.
TC
TC0
000-007
0
00.0003
REUNT
-
000
2
00.00
INHINT
-
000
2
00.0006
EXTEND
-
000
2
01.0
CCS
ccso
010-011
0
010-011
2
01.2
TCF
TCF0
012-017
0
01.4
01.6
02.0
DAS
DAS0
020-021
0
DAS1
020-021
1
STD2
020-021
2
02. 2
LXCH
LXCH0
022-023
0
STD2
022-023
2
02.4
INCR
INCR0
024-025
0
STD2
024-025
2
02.6
ADS
ADS0
026-027
0
STD2
026-027
2
03.
CA
CAO
030-037
0
STD2
030-037
2
04.
CS
CSO
040-047
0
STD2
040-047
2
05.0
NDX
NDXO
050-051
0
NDX1
050-051
1
(Sheet 1 of 5)
4-68
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Table 4-V. Subinstructions
Order
Mnemonic
Mnemonic
Register
Stage
Code
Operation
Subinstruction
SQ
Counter
c(SQ)
Code
Code
Display
Display
REC
IULAR INSTRUCTS
IS
05.0017
RESUME
NDX0
050-051
0
RSM3
050-051
3
05.2
DXCH
DXCH0
052-053
0
DXCH1
052-053
1
STD2
052-053
2
05.4
TS
TS0
054-055
0
STD2
054-055
2
05.6
XCH
XCH0
056-057
0
STD2
056-057
2
06.
AD
ADO
060-067
0
STD2
060-067
2
07.
MSK
MASK0
070-077
0
STD2
070-077
2
10.0
READ
READ0
100
0
STD2
100
2
10. 1
WRITE
WRITE0
101
0
STD2
101
2
10.2
RAND
RAND0
102
0
STD2
102
2
10.3
WAND
WANDO
103
0
STD2
103
2
10.4
ROR
RORO
104
0
STD2
104
2
10.5
WOR
WORO
105
0
STD2
105
2
(Sheet 2 of 5)
4-69
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MANUAL
Table 4-V. Subinstructions
Order
Mnemonic
Mnemonic
Register
Stage
Code
Operation
Subinstruction
SQ
Counter
c(SQ)
Code
Code
Display
Display
RE
GULAR INSTRUCTION
S
10.6
RXOR
RXORO
106
0
STD2
106
2
10.7
RUPT
RUPT0
107
0
RUPT1
107
1
STD2
107
2
11.0
DV
DV0
110-111
0
DV1
110-111
1
DV3
110-111
3
DV7
110-111
7
DV6
110-111
6
DV4
110-111
4
STD2
110-111
2
11.2
BZF
BZF0
112-117
0
11.4
(Plus Zero)
11.6
BZF
BZF0
112-117
0
(Non- Zero)
STD2
112-117
2
12.0
MSU
MSU0
120-121
0
STD2
120-121
2
12.2
QXCH
QXCH0
122-123
0
STD2
122-123
2
12.4
AUG
AUG0
124-125
0
STD2
124-125
2
12.6
DIM
DIM0
126-127
0
STD2
126-127
2
13.
DCA
DC A0
130-137
0
DCA1
130-137
1
STD2
130-137
2
(Sheet 3 of 5)
4-70
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MANUAL
Table 4-V. Sub instructions
Order
Code
c(SQ)
Mnemonic
Operation
Code
Mnemonic
Sub instruction
Code
Register
SQ
Display
Stage
Counter
Display
RE
GULAR INSTRUCTIONS
14.
DCS
DCSO
140-147
0
DCS1
140-147
1
STD2
140-147
2
15.
NDX
NDXXO
150-157
0
NDXX1
150-157
1
16.0
su
SUO
160-161
0
STD2
160-161
2
16.2
BZMF
BZMFO
162-167
0
16.4
(Zero or
Negative)
BZMF
BZMFO
162-167
0
(Non- Zero
STD2
2
and Positive)
17.
MP
MPO
170-177
0
MP1
170-177
1
MP3
170-177
3
INVOLUNTARY INSTRUCTIONS
00.
GOJ
GOJ1
000
1
TCO
000
0
10. 7
RUPT
RUPTO
107
0
RUPT1
107
1
STD2
107
2
None
PINC
PINC
None
None
None
MINC
MINC
None
None
None
DINC
DINC
None
None
None
MCDU
MCDU
None
None
None
SHINC
SHINC
None
None
None
SHANC
SHANC
None
None
(Sheet 4 of 5)
4-71
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MANUAL
Table 4-V. Subinstructions
Order
Mnemonic
Mnemonic
Register
Stage
Code
Operation
Subinstruction
SQ
Counter
c(SQ)
Code
Code
Display
Display
PERIPHERAL INSTRUCTIONS
00
TCSAJ
TCSAJ3
000
3
STD2
000
2
None
FETCH
FETCH0
None
0
FETCH1
None
1
None
STORE
STOREO
None
0
STORE 1
None
1
None
INOTRD
INOTRD
None
None
None
INOTLD
INOTLD
None
None
(Sheet 5 of 5)
pulse RSC reads onto the write lines the content of register CP whose address is con¬
tained in register S. Other read control pulses place data on the write lines directly
through the sequence generator. For instance, control pulse R15 causes the sequence
generator to place the octal quantity 000015 on the write lines.
4-5. 2. 5. 2 Write Control Pulses. Each write control pulse clears a register, then
writes data from the write lines into this register. Most write control pulses write
into a specific register such as control pulse WQ which always writes data into register
Q, but never into any other register. Control pulse WSC clears register CP specified
by the content of register S, then writes data into this register from the write lines.
4-5. 2.5. 3 Test Control Pulses. Test control pulses permit branching operations by
testing the contents of various registers. For instance, control pulse TMZ tests the
contents of a register for minus zero (octal 177777). If the register contains 177777,
flip-flop BR2 is set to logic ONE; otherwise, BR2 is set to logic ZERO.
4-5. 2. 5. 4 Direct Exchange Control Pulses. Direct exchange control pulses transfer
data from one area to another directly without using the write lines. Control pulse
A2X, for example, copies the content of register A directly into register X. Some di¬
rect exchange control pulses enter data from the sequence generator directly into
particular storage areas. Control pulse CP, for example, enters a logic ONE from the
sequence generator into the carry flip-flop of the adder.
4-5. 2. 5. 5 Special Purpose Control Pulses. Special purpose control pulses perform
various control functions such as generating read/write operations and resetting
counters. For instance, control pulse NISQ causes two other control pulses (RB and
WSQ) to be generated at time 12; control pulse RSTSTG resets the stage counter. All
control pulses are listed in table 4-VL
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Table 4- VI. Control Pulses
Pulse
Purpose
A2X
Enter bits 16 through 1 of register A directly (not via WL's) into bit
positions 16 through 1 of register X.
B15X
Enter a logic ONE into bit position 15 of register X.
Cl
Insert carry bit into bit position 1 of the adder.
CLXC
Clear register X if flip-flop BR1 contains a logic ZERO. (Used in
divide instruction. )
DVST
Advance the Gray code content of the stage counter by complementing
the content of the next higher bit position as shown below:
Binary Octal
000 0
001 1
011 3
111 7
110 6
100 4
EXT
Enter a logic ONE into bit position EXT of register SQ.
G2LS
Enter bits 16 through 4 and 1 of register G into bit positions 16, 15,
and 12 through 1 of register X. See control pulse ZAP.
KRPT
Reset interrupt priority cells.
L16
Enter a logic ONE into bit position 16 of register L.
L2GD
Enter bits 16 and 14 through 1 of register L into bit positions 16
through 2 of register G; enter a logic ONE (pulse MCRO) into bit
position 1 of register G.
MONEX
Clear register X, then enter logic ONE’S into bit positions 16
through 2.
MOUT
Generate one negative rate output pulse.
NEACOF
Permit end around carry upon completion of subinstruction MP3.
(Sheet 1 of 6)
4-73
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MANUAL
Table 4-VI. Control Pulses
Pulse
Purpose
NEACON
Inhibit end around carry (also during WYD) until NEACOF.
NISQ
Load next instruction into register SQ. Also frees certain restric¬
tions; permits execution of instruction RUPT and counter instructions.
See control pulses RB and WSQ.
PIFL
Prevent interflow on control pulse WYD if bit position 15 of register
L contains a logic ONE; block writing into bit position 1 of register
Y. See control pulse WYD.
PONEX
Clear register X, then enter a logic ONE into bit position 1.
POUT
Generate one positive rate output pulse.
PTWOX
Clear register X, then enter a logic ONE into bit position 2.
R15
Place octal 15 on WL's.
R1C
Place octal 177776 (minus one) on WL's.
RA
Read bits 16 through 1 of register A to WL's 16 through 1.
RAD
Read address of next cycle. RAD appears at the end of an instruc¬
tion and is normally interpreted as RG. If the next instruction is
INHINT, RELINT, or EXTEND, RAD is interpreted as RZ and ST2
instead.
RB
Read bits 16 through 1 of register B to WL's 16 through 1.
RBBK
Read bits 16 and 14 through 11 of register FB to WL's 16 and 14
through 11 and bits 11, 10, and 9 of register EB to WL's 3, 2, and 1.
RBI
Place octal 1 on WL's.
RB1F
Place octal 1 on WL's if flip-flop BR1 contains a logic ONE.
RB2
Place octal 2 on WL's.
RC
Read the complemented contents of register B (bits 16 through 1 of
C) to WL's 16 through 1.
(Sheet 2 of 6)
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MANUAL
Table 4-VI. Control Pulses
Pulse
Purpose
RCH
Read the contents of the input or output channel specified by the con¬
tents of register S; bit 16 is read to WL's 16 and 15 and bits 14
through 1 are read to WL's 14 through 1.
REB
Read bits 11, 10, and 9 of register EB to WL's 11, 10, and 9. See
control pulse RSC.
RFB
Read bits 16 and 14 through 11 of register FB to WL's 16 and 14
through 11. See control pulse RSC.
RG
Read bits 16 through 1 of register G to WL's 16 through 1.
RL
Read bit 16 of register L to WL's 16 and 15, and bits 14 through 1 to
WL's 14 through 1.
RL10BB
Read low 10 bits of register B to WL's 10 through 1.
RQ
Read bits 16 through 1 of register Q to WL's 16 through 1.
RRPA
Place on WL's the address of the priority program requested.
RSC
Read the content of register CP defined by the content of register S;
bits 16 through 1 are read to WL's 16 through 1.
RSCT
Place on WL's the address of the counter to be incremented.
RSTRT
Place octal 4000 (start address) on WL's.
RSTSTG
Reset the stage counter.
RU
Read bits 16 through 1 of adder output gates (U) to WL's 16 through 1.
RUS
Read bit 15 of adder output gates (U) to WL's 16 and 15, bits 14
through 1.
RZ
Read bits 16 through 1 of register Z to WL's 16 through 1.
ST1
Set stage 1 flip-flop to logic ONE at next time 12.
ST2
Set stage 2 flip-flop to logic ONE at next time 12.
(Sheet 3 of 6)
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MANUAL
Table 4-VI. Control Pulses
Pulse
Purpose
STAGE
Execute next subinstruction as defined by the content of the divide
stage counter.
TL15
Copy bit 15 of register L into flip-flop BR1.
TMZ
Test for minus zero: if bits 16 through 1 are all logic ONE’S, set
flip-flop BR2 to logic ONE; otherwise set BR2 to logic ZERO.
TOV
Test for overflow: set flip-flops BR1 and BR2 to 01 if positive over¬
flow, to 10 if negative overflow.
TPZG
Test content of register G for plus zero: if bits 16 through 1 are all
logic ZERO'S, set flip-flop BR2 to logic ONE: otherwise do not
change content of BR2.
TRSM
Test for the resume address (0017) during instruction NDX.
TSGN
Test sign (bit 16): if a logic ZERO, set flip-flop BR1 to logic ZERO;
if a logic ONE, set flip-flop BR1 to logic ONE.
TSGN2
Test sign (bit 16): if a logic ZERO, set flip-flop BR2 to logic ZERO;
if a logic ONE, set flip-flop BR2 to logic ONE.
TSGU
Test sign (bit 16) of sum contained in adder output gates (U): if a
logic ZERO, set flip-flop BR1 to logic ZERO; if a logic ONE, set
flip-flop BR1 to logic ONE.
U2BBK
Enter bits 16 and 14 through 11 of output gates U directly into regis¬
ter FB and bits 3, 2, and 1 of gates U into bits 11, 10, and 9 of reg¬
ister EB.
WA
Clear register A and write the contents of WL's 16 through 1 into bit
positions 16 through 1.
WALS
Clear register A and write the contents of WL's 16 through 3 into bit
positions 14 through 1; if bit position 1 of register G contains a logic
ZERO, the content of bit position 16 of register G is entered into bit
position 16 and 15 of register A; if bit position 1 of register G con¬
tains a logic ONE, the content of output gate U 16 of the adder is
entered into bit positions 16 and 15 of register A; clear bits 14 and 13
of register L and write the contents of WL's 2 and 1 into bit positions
14 and 13. See control pulse ZAP.
(Sheet 4 of 6)
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MANUAL
Table 4-VI. Control Pulses
•
Pulse
Purpose
WB
Clear register B and write the contents of WL's 16 through 1 into bit
positions 16 through 1.
•
WBBK
Clear registers EB and FB and write the content of WL's 16 and 14
through 11 into register FB and content of WL's 3, 2, and 1 into
register EB. See control pulse WSC.
WCH
Clear the channel specified by the contents of register S (bits 9
through 1) and write the contents of WL's 16 through 1 into this
channel.
WEB
Clear register EB and write the contents of WL's 11, 10, and 9 into
bit positions 11, 10, and 9. See control pulse WSC.
WFB
Clear register FB and write the content of WL's 16 and 14 through 11
into bit position 16 and 14 through 11. See control pulse WSC.
•
WG
Clear register G and write the contents of WL's 16 through 1 into bit
positions 16 through 1 (except if register S contains octal addresses
20 through 23).
WL
Clear register L and write the contents of WL's 16 through 1 into bit
positions 16 through 1.
WOVR
Test for positive overflow. If register S contains 0025, counter 0024
is incremented; if register S contains 0026, 0027, or 0030, instruc¬
tion RUPT is executed.
WQ
Clear register Q and write the contents of WL's 16 through 1 into bit
positions 16 through 1.
•
WS
Clear register S and write the contents of WL's 12 through 1 into bit
positions 12 through 1.
•
WSC
Clear the CP register specified by the contents of register S and
write the contents of WL's 16 through 1 into bit positions 16 through
1 of this register.
WSQ
Clear register SQ and write the contents of WL's 16 and 14 through 10
into bit positions 16 and 14 through 10, copy the content of the extend
flip-flop into bit position EXT of register SQ. See control pulse NISQ.
A
(Sheet 5 of 6)
4-77
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MANUAL
Table 4-VI. Control Pulses
Pulse
Purpose
WY
Clear registers X and Y; write the contents of WL’s 16 through 1 into
bit positions 16 through 1 of register Y.
WY12
Clear registers X and Y; write the contents of WL’s 12 through 1 into
bit positions 12 through 1 of register Y.
WYD
Clear registers X and Y; write the contents of WL's 16 and 14
through 1 into bit positions 16 and 15 through 2 of register Y; write
the content of WL 16 into bit position 1 of register Y except in SHINC
sequence, or unless bit 15 of register L is a logic ONE at PIFL, or
if end around carry is inhibited (NEACON).
WZ
Clear register Z and write the contents of WL's 16 through 1 into bit
positions 16 through 1.
Z15 Enter a logic ONE into bit position 15 of register Z.
Z16 Enter a logic ONE into bit position 16 of register Z.
ZAP Generate control pulses RU, G2LS, and WALS.
ZIP Generate control pulses A2X and L2GD; also perform read/write
operations depending on the content of bit positions 15, 2, and 1 of
register L as shown:
L15
L2
LI
Read
Write
Carry
Remember
0
0
0
_
WY
_
_
0
0
1
RB
WY
-
-
0
1
0
RB
WYD
-
-
0
1
1
RC
WY
Cl
MCRO
1
0
0
RB
WY
-
-
1
0
1
RB
WYD
-
-
1
1
0
RC
WY
Cl
MCRO
1
1
1
-
WY
-
MCRO
ZOUT
Generate no rate output pulse.
(Sheet 6 of 6)
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4-5. 2. 5. 6 Action. An action is a set of control pulses. By definition, a set may con¬
tain from zero to any number of control pulses. Each control pulse set is produced for
a 0. 977 microsecond period. Twelve control pulse sets or actions are produced during
one memory cycle time (11.977 microseconds). Control pulse sets are coincident with
time pulses T01 through T12. For example, action 6 of subinstruction STD2 occurs
at time 6 and consists of the control pulse set RU and WZ which copies the contents
of the adder output gates (U) into register Z. Table 4-VII lists the control pulses
generated during the execution of each subinstruction. The subinstructions are
arranged by order code number. The binary content of register SQ and the stage
counter are listed in table 4-VII. The coincidence of a subinstruction command and a
time pulse as STD2 and T06, is referred to as a crosspoint.
4-5. 2.6 Data Transfer Diagrams. The LGC instructions are described by subinstruc¬
tion data transfer diagrams which relate data flow to LGC hardware. Figures 4-20
through 4-116 contain data transfer diagrams for each subinstruction and a diagram for
each branch operation except for those in the multiply and divide subinstructions. The
quantities shown on these diagrams reflect typical operation conditions. The diagrams
are arranged according to order code listed in table 4-V.
Symbols FM and EM at the top of the diagrams designate fixed and erasable mem¬
ory, respectively, and CH refers to the channel locations. The octal quantities shown
in FM and EM represent 15 bit words and those shown in CH represent 16 bit words.
Register S is a 12 bit address register. Register G is a 6 bit memory buffer register.
Register B is a 16 bit terminal register containing a direct (B) and complement (C)
output side. Registers A and L are 16 bit accumulators, Q is a 16 bit return address
register, and register Z is a 16 bit program counter. Registers X and Y, output gates
U, and flip-flop Cl comprise the adder. Registers X and Y, and the output gates U con¬
tain 16 bit positions; Cl is the end around carry flip-flop. U always contains the sum
of c(X) + c(Y) + c(CI). Register SQ is a 7 bit sequence register. Not shown on these
diagrams are the 3 bit stage counter and the 2 bit branch register. The content of
these registers is specified by notes at the bottom of the data transfer diagrams.
Data shown in the registers prior to time 1 indicate typical starting conditions.
Data in the ellipses indicate write line information. The information passing between
FM or EM and G does not use the write lines and is therefore indicated by a direct
path. Flow lines are not shown for the data which is gated from one register to another
by a single control pulse such as A2X or L2GD. Broken flow lines indicate conditional
data flow which is dependent on the content of register S.
4-79/4-80
!
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
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MANUAL
Table 4-V11. Subinstruction Codes
and Control Pulses
Subinstruction
c(S0)
c (ST)
Actions
Remarks
Command
EXT
16 14.13
12.1U0
3,2.1
1
2
3
4
5
6
7
8
9
10
11
12
STD2
X
XXX
XXX
010
RZ
RSC
*
RU
RAD
Follows any subinstruction which sets c (ST) = 010
WY12
WG
WZ
WB
with control pulse ST2. Followed by next instruction.
Cl
NISQ
i
(
WS
,
See note A.
TCO
0
0 0 0
XXX
000
RB
RSC
RZ
RU
RAD
Followed by instruction to which control is transferred.
WY12
WG
WQ
WZ
WB
See note A
Cl
NISQ
WS
CCSO
0
0 0 1
oox •
000
RL10BB
RSC
RG
RZ
RU
RB
WY
|ru
/j\ Ifc(BR) = 00 at action 5, c(G) is positive
WS
WG
WB
WY12
WZ
WG
ST2
WA
non-zero.
TSG
A -
WS
>
=o
CD
/2\ If c(BR) = 01 at action 5. c(G) is plus zero.
tm;
MON EX
TP2
/2\ PONEX
Cl
/?\ Ifc(BR) = 10 at action 5. c(G) is negative
A -
non-zero.
f
/3\ P TV/OX
A
fi\ Ifc(BR) - 11 at action 5. c(G) is minus zero.
MON EX
i •
AS PONEX
c3 1
0
Followed by STD2.
PTWOX
TCFO
0
0 0 1
01 X
000
RB
RSC
RU
RAD
Followed by instruction to which control is transferred
0
0 0 1
1 0 X
000
WY1 2
WG
1
WZ
WB
See note A
0
0 0 1
1 1 X
000
Cl
NISQ
i
l
WS
- 1
(Sheet 1 of 13)
4-81/4-82
ND-1021042
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM MANUAL
to
Table
and C
4-VII. Subinstruction Codes
ontrol Pulses
Subinstruction
Command
c (SO)
c (ST)
Actions
Remarks
EXT 16.14.13 12.11.10
3.2.1
1
2
3
4
5
6
7
8
9
10
11
12
DASO
0 0 1 0 0 0 X
000
RL10BB
WS
WY 1 2
MONEX
Cl
RSC
WG
RA
WB
RL
WA
R
W
U
L
RG
WY
A2X
RB
WA
RL
WB
RU
WSC
WG
TOV
RA
WY
ST1
A -
/S\ PONEX
/3\ MONEX
RU
WA
/j\ If c (BR) = 00 at action 9, U 16. 15 = 0 0 or 1 1.
/?\ If c(BR) = 01 at action 9, U 16.15 = 01 .
/j\ If c(BR) = 10 at action 9. U 16.15 = 10.
Followed by DAS1 .
DAS1
0 0 1 0 00 X
1
001
RL10BB
WS
RSC
WG
R
W
4
i
RU
WG
WSC
TOV
WA
A -
/2\ RBI
/3\ R1C
RZ
WS
ST2
RC
TMZ
A V/L
A -
£
£
> -
RU
WA
/j\ If c ( BR) = OOat action 7, U 16.15 = OOor 11 .
/?\ If c(BR) = 0 1 at action 7. U 16.15 = 01 .
/3\ If c(BR) = 1 0 at action 7. U16.15 = 10.
/j\ If c ( BR) = X 0 at action 9. c(B) * 177777.
/fi\ If c ( BR) = X 1 at action 9. c (B) = 17777.
Followed by STD2
LXCHO
0 010 01 X
000
RL10BB
WS
RSC
WG
RL
WB
R
W
RB
WSC
WG
RZ
WS
ST2
Followed by STD2.
INCRO
0 0 10 1 ox
000
RL10BB
WS
RSC
WG
RG
WY
TSGN
TMZ
TPZG
PONEX
RU
WSC
WG
WOVR
RZ
WS
ST2
TSGN. TMZ. and TPZG at action 5 have no effect.
At action 7, WOVR requests RUPT if c(S) is 0026, 0027,
or 0030 and U16.15 = 01
Followed by STD2
(Sheet 2 of 13)
4-83/4-84
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
I
Table 4- VII. Subinstruction Codes
and Control Pulses
Subinstruction
c(SQ)
c (ST)
Actions
Remarks
Command
EXT
16.14.13
12.11.10
3.2.1
1
2
3
4
5
6
7
8
9
10
11
12
ADSO
0
0 1 0
1 1 X
000
RL10BB
RSC
RG '
RU
WA
RZ
RC
RU
/j\ If c(BR) = 00 at action 7. U 16.15 = 00 or 1 1 .
WS
WG
WY
WSC
A -
WS
TMZ
WA
/2\ If c (BR) = 0 1 at action 7. U16.15 = 01.
A2X
WG
ST2
i
TOV
/j\ RBI
/j\ Ifc(BR) = 1 Oat action 7, U 16,15 = 10.
RC and TMZ at action 9 have no effect.
^ R1C
Followed by STD2.
CAO
0
0 1 1
XXX
000
RSC
RG
RZ
RB
RB
Followed by STD2
WG
WB
WS
WG
WA
ST2
CSO
0
1 0 0
XXX
000
RSC
RG
RZ
RB
RC
Followed by STD2
WG
WB
WS
WG
WA
ST2
NDXO
0
1 0 1
OOX
000
RSC
TfW
RG
RZ
RB
ST1
Normally followed by NDX1. Followed by RSM3
WG
1
WB
WS
WG
ifc(S) = 0017 (RESUME) at action 5.
NDX1
0
1 0 1
OOX
001
RZ
RSC
RB
RA
RZ
I
RU
RG
RU
RB
RU
Followed by indexed basic instruction.
WY12
WG
WZ
WB
WA
WZ
WY
WS
WA
WB
Cl
NISQ
1
A2X
RSM3
0
1 0 1
OOX
0 1 1
R15
RSC
RG
RB
RAD
Followed by instruction at return address.
WS
WG
WZ
WG
WB
See note A.
NISQ
1
WS
DXCHO
0
1 0 1
01 X
000
RL10BB
RSC
RL
RG 1
RB
RU
ST1
Control pulse Cl at action 1 causes 000001 plus
WS
WG
WB
WL l
WSC
WS
177776 to result in 000000 instead of 177777
WY12
WG
WB
Followed by DXCH1
MONEX
Cl
!
(Sheet 3 of 13)
4-85/4-86
Subinstruction
Command
DXCH1
TSO
c (SQ)
EXT 16 14.13 12,11.10
0 10 1 01 X
0 10 1 1 OX
c (ST)
3.2.1
00 1
000
RL10BB
WS
RL10BB
WS
RSC
WG
RSC
WG
RA
WB
RA
WB
TOV
XCHO
0 10 1 1 1 X
000
RL10BB
WS
RSC
WG
RA
WB
ADO
MSKO
DVO
0 110 XXX
000
RSC
WG
0 111 XXX
000
RSC
WG
RA
WB
1 001 00X
000
RA
WB
TSGN
TMZ
A RC
WA
TMZ
DVST
A DVST
RU
WB
STAGE
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
,A!
ND-1021042
MANUAL
Table 4-VII. Subinstruction Codes
and Control Pulses
Actions
Remarks
WY
B15X
RU
WL
TOV
A -
A TSGN
/j\ RB
A RC
Z16
RG
RSC
WB
TSGN
A PON EX
A ~
A rb
WA
A RC
WA
Z15
RL
WYD
RG
WL
TSGU
DVST
RU
WB
STAGE
A CLXC
/fp\ RB1F
/j\ If c (BR) = XO at action 4, c (A) at action 2
of DVO is non-zero.
/2\ Ifc(BR) = XI at action 4. c (A) at action 2
of DVO is minus zero.
/5\ If c(BR) = OX at action 5, A16 = 0 at
action 2 of DVO or L 16 = 0 at action 4 of DV1
A If c(BR) = 1 X at action 5. A16 = 1 at
action 2 of DVO or L 16 = 0 at action 4 of DV1
/5\ If c (BR) = XO at action 8. U 16. 15 = 00,
10. or 11.
/6\ If c (BR) = XI at action 8, U16, 15 = 01.
A If c(BR) = OX at action 9. G16 = 0.
/8\ If c(BR) = 1 X at action 9. G16 = 1
A If c(BR) = OX at action 2, U16 = 0.
A If c(BR) = IX at action 2. U16 = 1
Followed by DV3 after action 3.
WYD
A2X
PIFL
TSGU
A CL^XC
RB
WYD
A2X
PIFL
WL
TSGU
A CLXC
A RB1F
RB
WYD
A2X
PIFL
WL
TSGU
A! CLXC
i
A RB1F
A If c(BR) = OX at action 5. 8. or 11, U16 = 0.
A If c ( BR) = 1 X at action 5. 8, or 11, U 16 = 1
(Sheet 5 of 13)
DVl
(cont)
0 0 1
00 X
00 1
0 0 1
00 X
001
0 0 1
00X
Oil
L2GD
RB
WYD
A2X
PIFL
Subinstruction
c(SQ)
c (ST)
Command
EXT 16.14,13 12,11,10
3.2.1 1
4-89/4-90
Table 4- VII. Subinstruction Codes
and Control Pulses
LEM PRIMARY GUIDANCE, NAVIGATION,
ND 1021042
MANUAL
Subinstruction
Command
DV3
(contl
c(SQ)
EXT 16 14,13 12.11.10
00 X
c(ST)
0 1 1
L2CD
RB
WYD
A2X
PIFL
RG
WL
TSGU
DVST
/j\ CLXC
/4\ RB1F
RU
WB
STAGE
Actions
Remarks
/S\ If c(RR) = OX at action 2 U16 = 0
/4\ If c (BR) = 1 X at action 2, U16 = 1
Followed by DV7 after action 3.
00 X
DV7
(cont)
0 0 1
00X
1 1 1
L2GD
RB
WYD
A2X
PIFL
WL WB
TSGU STAGE
DVST
/l\ CLXC
/j\ RB1F
RB
WYD
A2X
‘PIFL
A
A
WL
TSGU
CLXC
RB1F
L2GD
RB
WYD
A2X
PIFL
/l\ If c (BR) = OX at action 5, 8. 11, or 2. U16 = 0
/j\ If c (BR) = 1 X at action 5. 8, 11, or 2, U16 = 1,
Followed by DV6 after action 3.
4-91/4-92
' RG
WL
TSGU
/P\ CLXC
/j\ RB1F
(Sheet 6 of 13)
f
<
LEM PRIMARY GUIDANCE NAVIGATION AND CONTROL SYSTEM
—
ND-1021042
MANUAL
Subinstruction
Command
c(SQ)
EXT 1614.13 12,11.10
c (ST)
oox
1 1 0
DV6
icont)
0 0 1
OOX
1 1 0
0 0 1
OOX
100
10
IT
- . -
L2GD
1 RG
RB
WL
WYD
! TSGU
A2X
/j\ CLXC
PIFL
/}\ RB1F
Table 4-VII. Subinstruction Codes
and Control Pulses
Remarks
/j\ If c(BR) - OX at action 5, 8, 11, or 2, U16 = 0.
/2\ Ifc(BR) = IX at action 5, 8, 11. or 2, U16 = 1
Followed by DV4 after action 3.
L2GD
RB
WYD
A2X
PIFL
RG
WL
TSGU
DVST
</j\ CLXC
/g\ RB1F
RU
WB
STAGE
A2X
PIFL
RZ
TOV
&
—
A
RC
WA
A
RC
WA
RZ
WS
ST2
TSGN
RSTSTG
Actions
L2GD
RB
WYD
A2X
PIFL
RG
WL
TSGU
/j\ CLXC
/j\ RB1F
A c
^ RB F
RG
WL
TS( J
/j\ CL) C
,4\ RC
/l\ Ifc(BR) = OX at action 5, U16 = 0
/?\ If c (BR) = 1 X at action 5, U 16 = 1.
SS lf c (BR) = 00 at action 7. U16.15 = 00 or 1 1
/4\ If c (BR) = 01 at action 7, U 16 . 15 = 01.
/5\ If c (BR) = 1 0 at action 7. U 16. 15 = 1 0.
/6\ Ifc(BR) = OX at action 10, Z16 = 0
/l\ Ifc(BR) = IX at action 10. Z16 = 1
L2GD
RB
WYD
A2X
PIFL
(Sheet 7 of 13)
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
f Table 4-VII. Subinstruction Codes
and Control Pulses
Subinstruction
Command
c(SQ)
c (ST)
'
Actions
Remarks
EXT 16.14.13 12,11.10
3.2.1
1
2
3
4
5
6
7
8
9
10
1
1
12
BZFO
1 001 0 1 X
1 0 0 1 1 OX
1 0 0 1 1 1 X
000
000
000
RSC
WG
RA
WG
TSGN
TMZ
TPZG
A
A iJ
WY12
Cl
A -
A RU
wz
rz
WS
ST2
/S\ RAD
WB
WS
NISQ
/j\ If c(BR) = XO at action 4. c(G) * 000000.
/2\ If c(BR) = XI at action 4, c(G) = 000000.
RSC at action 2,and TSGN and TMZ at action 3
have no effect. RAD causes only RG
If c(BR) = X0, BZFO is followed by STD2.
If c (BR) = X 1, BZFO is followed by instruction
to which control is transferred.
MSUO
1 0 f 0 0 0 X
000
RL10BB
WS
RSC
WG
RG
WB
RC
WY
Cl
A2X
RUS
WA
TSGN
RZ
WS
ST2
RB
WG
A -
A
WY
MONEX
R
W
US
A
/l\ If c(BR) = OX at action 7, U15 0.
/h Ifc(BR) = IX at action 7. U15 1.
Followed by STD2 .
QXCHO
1 0 10 01 X
000
RL10BB
WS
RSC
WG
RQ
WB
RG
W Q
RB
WSC
WG
RZ
WS
ST2
Followed by STD2.
AUGO
1 010 10X
000
RL10BB
WS
RSC
WG
RG
WY
TSC
TM 1
TP.
i
G
/l\ PONEX
/2\ MONEX
RU
WSC
WG
WOVR
RZ
WS
ST2
/l\ Ifc(BR) = OX at action 6. G16 = 0.
/2\ If c (BR) = IX at action 6, G16 = 1.
TMZ and TPZG at action 5 have no effect. At action 7,
WOVR requests RUPT if c(S) is 0026. 0027, or 0030 and
U 16,15 = 01. Foil wed by STD2
DIMO
1 0 10 1 1 X
000
RL10BB
WS
RSC
WG
RG
WY
TSG
TMZ
TPZ
N
G
/l\ MONEX
/2\ PONEX
A -
RU
WSC
WG
WOVR
RZ
WS
ST2
A If c (BR) = 00 at action 6, c(G) is positive non-zero.
/2\ If cfBR) = 10 at action 6. c(G) is negative
non-zero.
/?\ If c ( BR) = 01 or 11 at action 6. c (G) is plus
or minus zero WOVR at action 7 has no affect.
Followed by STD2
DCAO
1 011 XXX
000
RB
WY12
MONEX
Cl
RSC
WG
RG
WB
RU
WS
RB
WG
RB
WL
ST1
Followed by DCA1.
(Sheet 8 of 13)
4-95/4-96
*
ND 1021042
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM MANUAL
Table 4- VII. Subinstruction Codes
and Control Pulses
Subinstruction
Command
c(SQ)
c (ST)
Actions
Remarks
EXT
16.14.13
12.11.10
3.2.1
1
2
3
4
5
6
7
8
9
10
11
12
DCA1
1
0 1 1
XXX
00 1
RSC
RG
RZ
RB
RB
Followed by STD2
WG
WB
WS
WG
WA
ST2
DCSO
1
1 0 0
XXX
000
RB
RSC
RG
RU
RB
RC
Followed by DCS1
WY12
WG
WB
WS
WG
WL
MONEX
ST1
Cl
*
i
DCS1
1
1 0 0
XXX
001
RSC
RG
RZ
RB
RC
Followed by STD2.
WG
WB
WS
WG
WA
ST2
NDXXO
1
1 0 1
XXX
000
RSC
RG
RZ
RB
ST1
Followed by NDXX1.
WG
WB
WS
WG
NDXX1
1
1 0 1
XXX
00 1
RZ
RSC
RB
RA
R2
RU
RG
RU
RB
RU
Followed by an indexed extra code instruction
WY12
WG
WZ
WB
WA
WZ
WY
WS
WA
WB
Cl
NISQ
A2X
EXT
SUO
1
1 1 0
oox
000
RSC
RG
RZ
RB
RC
RU
Followed by STD2.
WG
WB
WS
WG
WY
WA
•
ST2
A2X
BZMFO
1
1 1 0
01 X
000
RSC
RA
TPZG
A -
A -
A RZ
A Ifc(BR) = 00 at action 4, c(G) is positive
1
1 1 0
10X
WG
WG
WS
non-zero.
1
1 1 0
1 1 X
TSGN
A RU
ST2
A If c (BR) = 0 1 at action 4. c (G) = 000000
TMZ
/2\ RB
A RA°
WY12
WZ
WB
/3\ If c (BR) = 10 at action 4, c (G) is negative
Cl*
WS
RSC at action 2 and TMZ at action 3 have no
NISQ
effect. RAD causes only RG.
A RB
A RU
A RAD
If c(BR) = 00, BZMFO is followed by STD2
WY12
WZ
WB
If c(BR) = 01 or 1 1, BZMFO is followed by
Cl
WS
instruction to which control is transferred
L
NISQ
(Sheet 9 of 13)
4-97/4-98
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 4- VII. Subinstruction Codes
and Control Pulses
Snbinstruction
Command
c(SQ)
c (ST)
!
Actions
Remarks
EXT
16.14.13
12.11.10
3.2.1
l
2
3
4
5
6
7
8
9
10
11
12
MPO
1
1 1 1
XXX
000
RSC
RA
A rb
RG
RZ
/3\ RB
RU
WA
/T\ If c(BR) = OX at action 3, A16 = 0.
WG
WB
WL
WB
WS
WY
WB
fiS-
/2\ Ifc(BR) = IX at action 3. A16 = 1.
TSGN
TSGN2
TSGN
ST1
/3\ If CIBR) = 00 at action 7. A16 = 0 and G16 = 0.
^ RC
A RB
NEACON
/4\ If c(BR) = 01 at action 7, A16 = 0 and G16 = 1.
WL
WY
/j\ RBI
Cl
RIC
/5\ If c(BR) = 10 at action 7. A16 = 1 and G16 = 0.
L16
/?\ RC
/6\ If c ( BR) = 11 at action 7. A16 = 1 and G 16 = 1.
WY
Cl
/l\ If c(BR) = OX at action 10. U16 = 0.
L16
/5\ If c(BR) = 1 X at action 10. U16 = 1 .
/6\ RC
WY
Followed by MP1 .
MP1
1
1 1 1
XXX
00 1
ZIP
ZAP
ZIP
ZAP
ZIP
ZAP
ZIP
ZAP
ZIP
ZAP
ZIP
Followed by MP3.
ST1
ST2
MP3
1
1 1 1
XXX
0 1 1
ZAP
ZIP
ZAP
RSC
RZ
RU
A -
RAD
RA
RL
A -
/l\ If c ( BR) = OX at action 6, U15 = 0.
NISQ
WG
WY12
WZ
A rb
WY
WB
/2\ If c(BR) = IX at action 6 U15 = 1.
Cl
TL15
WS
/2\ RU
NEACOF
WA
A2X
Followed by next instruction. See note A.
REAOO
1
0 0 0
000
000
RL10BB
RA
WY
RCH
RB
RA
RZ
Followed by STD2.
WS
WB
WB
WA
WB
WS
ST2
WRITEO
1
0 0 0
00 1
000
RL10BB
RA
WY
RCH
RA
RA
RZ
See note B Followed by STD2
WS
WB
WB
WCH
WB
WS
WG
ST2
RANDO
1
0 0 0
010
000
RL10BB
RA
RC
RCH
RC
RA
RC
RZ
Followed by STD2 .
WS
WB
WY
WB
RU .
WB
WA
WS
WA f
ST2
(Sheet 10 of 13)
4-99/4-100
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
i
ND-1021042
MANUAL
Table 4-VII. Subinstruction Codes
and Control Pulses
Subinstruction
Command
c(SQ)
c (ST)
k Actions
Remarks
EXT
16.14,13
12,11.10
3,2.1
1
2
3
4
-]
6
7
8
9
10
11
12
WANDO
1
0 0 0
01 1
000
RL10BB
RA
RC
RCH
RC |
RA
RC
RZ
See note B
WS
WB
WY
WB
RU
WB
WA
WS
Followed by STD2.
WA
WCH
ST2
RORO
1
0 0 0
100
000
RL10BB
RA
RB
RCH
RB
RA
RZ
Followed by STD2
WS
WB
WY
WB
RU
WB
WS
WA ,
ST2
WORO
1
0 0 0
101
000
RL10BB
RA
RB
RCH
RB
RA
RZ
See note B
WS
WB
WY
WB
RU
WB
WS
Followed by STD2.
WA
ST2
WCH
_
RXORO
1
0 0 0
1 1 0
000
RL10BB
RA
RC
RCH
RA 1
RG
RZ
RC
RU
RC
Followed by STD2
WS
WB
RCH
WB
RC 1
WB
WS
WG
WB
RG
WY
WG
_
ST2
WA
RUPTO
1
0 0 0
1 1 1
000
R15
RSC
1
RZ
ST1
RSC at action 2 has no effect.
WS
WG
WG
Followed by STD2
RUPT1
1
0 0 0
1 1 1
00 1
R15
RSC
RRPA
RZ
RB
RSC at action 2 has no effect
RB2
WG
WZ
WS
WG
Followed by STD2
WS
ST2
KRPT
GOJ1
0
0 0 0
XXX
00 1
RSC
I
RSTRT
Initiated by signal GOJAM RSC at action 2 has no
WG
WS
effect.
WB
Followed by TC 4000.
PINC
X
XXX
XXX
X X X
RSCT
RSC
RG
PONEX
RU
RB
See note C RSC at action 2. TSGN, TMZ. and
WS
WG
WY
WSC
WS
TPZG at action 5, and WSC at action 7 have no
tsgn'
WG
effect. At action 7. WOVR requests RUPT if c(S)
TMZ'I
WOVR
is 0026, 0027. or 0030 and U16.15 = 01. WOVR
TPZQf
l
requests PINC 0024 if c(S) is 0025 and U16.15 = 01.
(Sheet 11 of 13)
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 4-VII. Subinstruction Codes
and Control Pulses
Subinstruction
Command
c(SQ)
c (ST)
Actions
Remarks
EXT 16.14.13 12,11.10
3.2.1
1
2
3
4
5
6
7
8
9
10
1
1
12
MINC
X XXX XXX
XXX
RSCT
WS
RSC
WG
RG
WY
TSGN
TMZ
TPZG
MONEX
RU
WSC
WG
WOVR
RB
WS
See note C RSC at action 2, TSGN, TMZ, and
TPZG at action 5, and WSC and WOVR at action 7
have no effect.
PCDU
X XXX XXX
XXX
RSCT
WS
RSC
WG
RG
WY
TSGN
TMZ
TPZG
Cl
RUS
WSC
WG
WOVR
RB
WS
See note C RSC at action 2, TSGN, TMZ, and
TPZG at action 5. and WSC and WOVR at action 7
have no effect.
MCDU
X XXX XXX
XXX
RSCT
WS
RSC
WG
RG
WY
TSGN
TMZ
TPZG
MONEX
Cl
RUS
WSC
WG
WOVR
RB
WS
See note C. RSC at action 2, TSGN, TMZ. and
TPZG at action 5. and WSC and WOVR at action 7
have no effect.
DINC
X XXX XXX
XXX
RSCT
WS
RSC
WG
RG
WY
TSGN
TMZ
TPZG
AS MONEX
POUT
A\ PON EX
MOUT
AS ZOUT
RU
WSC
WG
WOVR
RB
WS
See note C
As Ifc(BR) = 00, c(G) is positive non-zero.
As If c(BR) = 10. c (G) is negative non zero
AS If c(BR) = 01, or 1 1, c(G) is plus or minus zero.
RSC at action 2, and WSC and WOVR at action 7 have
no effect.
SHINC
X XXX XXX
XXX
RSCT
WS
RSC
WG
RG
WYD
TSGN
RUS
WSC
WG
WOVR
RB
WS
See note C. RSC at action 2, and WSC and WOVR
at action 7 have no effect. At action 5. TSGN requests
RUPT if c (S) is 0045 and G16 = 1
SHANC
X XXX XXX
XXX
RSCT
WS
RSC
WG
RG
WYD
TSGN
Cl
RUS
WSC
WG
WOVR
RB
WS
See note C. RSC at action 2. and WSC and WOVR
at action 7 have no effect. At action 5. TSGN requests
RUPT if c(S) is 0045 and G16 = 1
(Sheet 12 of 13)
4-103/4-104
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
*
ND-1021042
MANUAL
Table 4-VII. Subinstruction Codes
and Control Pulses
Subinstruction
Command
ciSQ)
c (ST)
- i -
Actions
Remarks
EXT 16 14.13 12.11 10
3 2.1
1
2
3
4
5
6
7
8
9
10
1
12
TCSAJ3
X XXX XXX
XXX
RSC
WG
WS
WZ
ST2
See note D
Followed by STD2
INOTRD
X XXX XXX
XXX
WS
RSC
WG
RCH
RB
WS
See note D.
INOTLD
X XXX XXX
XXX
WS
RSC
WG
RCH
WCH
RB
WS
See note D.
FETCHO
X XXX XXX
000
RG
WS
RSC
WG
WY
ST1
WSC
|
WS
See note D .
Followed by FETCH1
FETCH1
X XXX XXX
001
RSC
WG
»
RG
RB
WS
U2BBK
RBBK
_
See note D
STOREO
X XXX XXX
000
RG
WS
RSC
WG
WY
ST1
WSC
WS
See note D.
Followed by STORE1
ST0RE1
X XXX XXX
001
RSC
WG
WSC
RG
RB
WS
U2BBK
WG
RBBK
See note D.
9
NOTES A lfc(Gi = 000003 (RELINT). 000004 (INHINT >. or 000006 (EXTENT), control pulse RAD causes the genera- c Counter instructions are executed after any time 12 provided an involuntary or peripheral instruction is not
lion of control pulses RZ and ST2. and subinstruction STD2 is executed next. If G contains any other being requested Each counter instruction delays program execution for one MCT
quantity control pulse RAD causes the generation of control pulse RG and the next instruction is executed
D. Peripheral instructions are initiated by a signal from the CTS or the PAC Normally the LGC time counter
B The ONE entered into bit position 1 0 of register S has no effect on addressing channel locations is stopped at time 12 before and after the execution of an instruction.
- 4 _ _ _
(Sheet 13 of 13)
4-105/4-10(5
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
40701
Figure 4-20. Subinstruction TCO, Data Transfer Diagram
4-107
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00006
,00006
CH
S
1540
WS
, 1541
6
001540 W6| 000000
000006
'000006
1
1
B
001540
> (£>00000) WB<
>001541 RB
1
1
A
RSC | (CW
54l)
L
RSC |
0
(ocn
^3) Rsc| *<>.£01526
z
001326
RSC 1 RZ • - (001
i26) WZA 001541 RZ (RAD)1
(00154?) (00
54M
u
001326
RU*00I54I
Y
001325 '
WYI2 001540
X
000000 • WYI2 000000
Cl
1 1
SO
000 100 WSQ1
rioi
TIME
1
2 3
4
5
6
7 8
STAGE
Cl
NISO
ST2 (RAD) SETS
COUNTER
SETS
CAUSES RB
STAGE COUNTER
IS SET
CARRY
AND WSQ
TO 010-
TO 000
FLIP-
AT TIME 12-
EXTPLS SETS
FLOP
RSC IS INHIBITED
BIT EXT OF SQ
BY ADORESS
1540 IN S
40702
Figure 4-21. Subinstruction TCO, with Implied Address Code EXTEND,
Data Transfer Diagram
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM*
'03777
03777
CH
S
0300 *WS 0300
WS,
6521
(000
300)
G
010300
WG| 000000
003777 «FG
WGA003777 1
'003777
(003777)
1
(003777)
B
010300
ilOBB 1 WGT 003777 (oO(
«j) »b1 rb
(oooood)
A
RScl
1
WA,
,003776
L
RSC +
Q
1
RSCJ
(003
Z
006521 RScl RZ'
1 WZ,
,006521
r
(^03
(ooe
52b (ooe
52l)
r
u
006521
RUi
006521
RU<
003776
Y
006520 WYl2
006521 WY
’003777
X
000000 WYI2« 000000 M0NEX*I77776
CI
1 0 1
SQ 010
TIME
STAGE
COUNTER
IS SET
TO 000
2
RSC IS
INHIBITED BY
ADDRESS
0300 IN S
5 6
TMZ, TPZG.
AND TSGN
SET C(BR) ■ 00
Cl SETS
CARRY
FLIP-FLOP
ST 2 SETS
STAGE
COUNTER
TO 010
40703
Figure 4-22. Subinstruction CCSO, Branch on Quantity Greater Than Plus Zero,
Data Transfer Diagram
4-109
LEM PRIMARY 6UI DANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
TIME
STAGE
COUNTER
IS SET
TO 000
2
RSC IS
INHIBITED BY
ADDRESS
0300 IN S
4 5
TMZ, TSGN,
AND TPZG
SET C (BR) = 01
10 II
ST2 SETS
STAGE
COUNTER
TO 010
Figure 4-23. Subinstruction CCSO, Branch on Minus Zero, Data Transfer Diagram
4-110
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
176544
i 76544
CH
S
0300
IWS 0300
WS
6523
(OOG
300)
G
010300
WG A OOOOOO
1
176544 • RG
WG A 176544
H76544
(^76544) (006
523) (l76544)
B
010300
1
'RLIOBB | WBTI76544
RbA RC
'001233
(OOOOOO)
A
RSC +
WA
,001233
L
1
RSC +
1
0
RSC +
1
(ooi'
z
006521 RSC* RZ# WZ
,006523
r
(och
232)
(ooe
52M (006
f>
u
006521
RU<
'006523
RUl
'001232
Y
006520 WYI2
006521 WY'
001233
X
OOOOOO PTWOX«000002 MONEX •177776
Cl
■ 0 1
TIME
1 2
3
4 5
6
7
8
9
10
STAGE
RSC IS
TSGN, TMZ,
Cl SETS
COUNTER
INHIBITED BY
AND TPZG
CARRY
IS SET
ADDRESS
SET CIBRMO
FLIP-FLOP -
TO 000
0300 IN S
ST2 SETS
STAGE
COUNTER
TO 010
40705
Figure 4-24. Subinstruction CCSO, Branch on Quantity Less Than Minus Zero,
Data Transfer Diagram
i
4-111
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
OOOOO
OOOOO
CH
S
0300
|WS 0300
WS,
6524
(oio
300)
G
010300
WG^ OOOOOO
oooooo _RG
WG A OOOOOO
OOOOOO
. (oooooo)
(oooooo)
B
010300
RLIOBB 1 WB tOOOOOO
Irb
(ooooo (j) (006
524)
A
JRSC
WA
,000000
L
|rsc
0
Irsc
(ooo
ooo)
z
006521 Af»SC «RZ wz
006524
(006
52l)
u
006521
RU'
006524 RU(
oooooo
Y
006520 WY,2 '
006521 WY *000000
X
oooooo # 000003 WY # QOOOOO
Cl
1 0
SO
010
TIME
1 2 3
4
5
6
7
e
9
10 II
STAGE
COUNTER
IS SET
TO OOO
RSC IS
INHIBITED BY
ADDRESS 0300
IN S
TPZG.TSGN
AND TMZ SET
C(BR) > II
ST2 SETS
STAGE COUNTER
TO OIO
40706
Figure 4-25. Subinstruction CCSO, Branch on Plus 0, Data Transfer Diagram
4-112
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
1
'26077 |
, 26077
CH
1
1
S
0521
1
1 WSi
6077
1 (p26
1
077)
G
003777 WG|000000
026077 ♦ RADI
>026077
1
1 (026
1
077)
B
003777 (OOOOOO) WB'
026077 RB <
1
A
RSc|
L
1
RSC|
0
RSC|
1
Z
000521 #RZ RSci WZ A 000522
(ooc
52?) (000522) (026
YT7)
u
003776
RU *000522
Y
003777 ’
WYI2 000521
X
177776 • WYI2 OOOOOO
Cl
<
SO
010 WSQ
r026
1
2
3
4
5
6
Cl
NISO
FIXED
SETS
CAUSES
MEMORY
CARRY
RB AND
STROBE IS
FLIP-
WSQ AT
INHIBITED
FLOP
TIME 12*
BY ADDRESS
RSC IS
INHIBITED
BY ADDRESS
0521 IN S
0521 IN S
40707
Figure 4-26. Submstruction STD2, Data Transfer Diagram
4-113
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
F M
EM
00004
00004
CH
S
0721
WS
1 0443
6
002421 WG^OOOOOO '
000004
1 000004
1
1
8
002421 (OOOOOO) WB
•000443 RB
1
1
A
RSc| (000
443)
L
RSC |
Q
RSC !
Z
000442 «RZ RSC 1 WZA000443 RZ(RAD) 1
(ooc
442) (000443) (000
443)
u
000442
Rui 000443
Y
000441 '
WYI2 000442
X
OOOOOO
Cl
•
SO
012 . WSO1
000
TIME
1
2
3
4 5
6
7
8
STAGE
Cl SETS
RSC IS
000004 IN
ST2 (RAD)
COUNTER
CARRY
INHIBITED
G SETS
SETS STAGE
IS SET
FLIP-
BY
INTERRUPT
COUNTER
TO 010
FLOP
ADDRESS
INHIBIT FLIP-
TO 010
0721 IN S -
FLOP
NISO CAUSES
R8 AND WSO
AT TIME 12
40708
Figure 4-27. Subinstruction STD2, with Implied Address Code INHINT,
Data Transfer Diagram
4-114
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
100003
i00003
CH
S
0667
WS
1 0552
G
002 A WG ^ 000000
r 000003
> 000003
|
1
B
002421 foOOOOO) WB 1
000552 RB
i
i
A
RSc| (000
552)
L
RSC*
1
Q
RSCf
1
Z
000551
iRZ RSci WZ A 000552 RZi
(RAD)
(ooc
55l) (0OO552) (000
552)
u
000551
RU* 000552
Y
000550
WYI2 000551
X
000000
Cl
'
SQ
012 WSO
000
TIME
STAGE
COUNTER
IS SET
TO 010
Cl SETS
CARRY
FLIP-FLOP
RSC IS
INHIBITED
BY ADDRESS
0667 IN S -
NISO CAUSES
RB AND WSO
AT TIME 12
000003
IN G RESETS
INTERRUPT
INHIBIT
FLIP-FLOP
ST2 ( RADI
SETS STAGE
COUNTER
TO 010
10 II 12
40709
Figure 4-28. Subinstruction STD2, with Implied Address Code RELINT,
Data Transfer Diagram
4-115
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
F M
T
EM
1
' 00006 |
00006
CH
1
1
S
1123
1
I ws
1124
1
1
G
OI2IOO WG^OOOOOO
' 000006 i
'000006
1
1
B
012100 (OOOOO^) WB<
001124 RB
1
A
012345 RSC } (00T
L
RSC !
1
0
RSC f
z
OOII23 1
iRZ RSC 4 WZA00II24 RZ <
(RAD)
(OOI
^23) (00M24) (00T
u
001123
RU #001124
1
Y
OOII22
WYI2 001123
X
000000 «WYI2 000000
Cl
'
SO
010 no wsq’
101
TIME
1
2 3
4
5
6 7
8 9
STAGE
COUNTER
IS SET
TO 010
Cl SETS
NISO CAUSES
FIXED MEMORY
ST 2 (RAD) SETS
CARRY
RB AND WSO
STROBE IS
STAGE COUNTER
FLIP-
AT TIME 12-
INHIBITED BY
TO 010-
FLOP
RSC IS
ADDRESS 1123
EXTPLS SETS
INHIBITED
IN S
BIT EXT OF SO
BY ADDRESS
1123 IN S
40710
Figure 4-29. Subinstruction STD2, with Implied Address Code EXTEND,
Data Transfer Diagram
4-116
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
• 22501
EM
CH
S
3725
WS A 2501
(022
50?)
6
013725 WG^ 000000
022501
• RAD
( 022
50N
B
013725 i
• RB (60OOOO) WB
r°22501 RB 022501
1
1
A
j RSC
L
|rsc
Q
(on
725) I RSC
Z
001526
Irsc vvz
,003726
(003726) (022
u
001526
RU (
003726
Y
001525
WYI2
003725
X
WYI2
000000 000000
Cl
' •
SQ
013 WSQ
022
TIME
STAGE Cl SETS NISO CAUSES
COUNTER CARRY RB AND WSQ
IS SET FLIP-FLOP AT TIME 12-
TO OOO RSC IS
INHIBITED BY
ADDRESS
3725 IN S
40711
Figure 4-30. Subinstruction TCFO, Data Transfer Diagram
4-117
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
40712
Figure 4-31. Subinstruction TCFO, with Implied Address Code EXTEND,
Data Transfer Diagram
4-118
IEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00045
37123
CH
S
0143
iWS 0143
(ooc
143)
G
020143
WG ^ 000000
000045 RG
1 WG
037123
1
1
B
020143
1
1 RLIOBB | WB *002731
R8 • WB
000142
(OOOOOO) (0027ji) (000
045) (p0273l) (OOO
^42) (037
123)
A
002731
RScj RaI 037056 ’•-(037056)
WA *002731
WSC
RA
WA
,002731
L
037056
RSci RL* -
WL
000142
RU
1 WSC
0
(ooo
I43) RSc|
WSC
Z
005345
RSci (OOO
^42)
W SC 1
(002
73^) (002
r
u
005345
RU i
000142
RU i
037123
RU1
002731
Y
005344 '
WI2 000143 WY
'000045 WY'
^002731
X
000000 *MONEX 177776 A2X *037056 WY«000000
Cl
■
SQ
020
TIME
1
2 3
4
5
6
7
8
9
10
II
STAGE
Cl SETS
RSC IS
TOV SETS
ST 1 SETS
CTR
CARRY FLIP-
INHIBITED BY
C( BR ) = 00 -
STAGE
IS SET
FLOP
ADDRESS 0143
WSC IS
COUNTER
TO UOO
IN S
INHIBITED
BY
ADDRESS
0143 IN S
TO 001
40713
Figure 4-32. Subinstruction DASO, without Overflow or Underflow,
Data Transfer Diagram
4-119
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
'00221 ,
,03152
CH
S
0143
IWS 0142
WS
i5345
(ooc
142)
G
037123
WG|000000 1
000221
>RG WG
,003152
1 003152
1
-1
B
000142
RLIOBB |
(oooooo)
(002
152) (oooooo) (005
345) (boo
DOO)
A
002731 RSC+
j
wscj
WAf OOOOOO
L
000142 RSCf (OOC
22j) WSC
wu
OOOOOO
Q
1
RSCj
WSC,
Z
1
005345 RSCi
WSC,
RZ<
u
002731
RUi
003152
Y
002731 WY'
1000221
X
OOOOOO A2X» 002731
Cl
SO
020
TIME
2
3
4
5
6
7
8 9 10
II
12
STAGE
RSC IS
WSC IS
RBI
ST2 SETS
COUNTER IS
INHIBITED BY
INHIBITED
AND
STAGE COUNTER
SET TO
0142 IN S
BY ADDRESS
RIC
TO 010
001
0142 IN S
PLACES
RC AND TMZ
TOV SETS
177777
SET C(BR) ■ 00
C(BR)«00
ON
WRITE
LINES
40714
Figure 4-33. Subinstruction DAS1, without Overflow or Underflow,
Data Transfer Diagram
4-120
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
T t
CH
1 1
1 1
S
0001
I 1
>WS 0001 I 1
(ooc
^ 1 1
>00l) I I
G
020001
WG
>062200 1 RGi
WGL
i04440l 1
B
020001
•RLIOBB
WBA020000
RB* WB,
O
0
0
O
O
0
(062
200) (020000)
(020000) (000
OOO)
A
020000
WA ^ - >v
RA* l62200-*-(l62200)
WAT020000
RAi
WAi
020001
L
062200
RSC(
i RL* - '
WL
000000
RLi
1 wsc
O
V
0
Q
(062
200)
Z
000500
(£oc
ooo)
(04<
4oj) (020
ooo) (02c
ooj)
(ooc
ooj)
u
000500
RU(
,000000
RU4
1044401
RU<
020001
Y
000477 '
WYI2 000001 WY1
062200 WY’
^020000
X
000000 •MONEX 177776 A2X«I62200 P0NEX»00000l
Cl
1 1
SO
020
TIME
1 2
3 4
5
6
7
8
9
10 1
STAGE
COUNTER
IS SET
TO OOO
Cl SETS
CARRY
FLIP-FLOP
ERASABLE
MEMORY
STROBE IS
INHIBITED
BY AOORESS
0001 IN S
TOV
SETS
C(BR)«OI
STI SETS
STAGE COUNTER
TO 001 -
ERASABLE
MEMORY STROBE
IS INHIBITED
BY AOORESS
0001 IN S
40715
Figure 4-34. Subinstruction DASO, with Overflow and Implied Address Code DDOUBL,
Data Transfer Diagram
4-121
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
T t
CH
1 1
1
S
OOOI
WS 0000 . WSi
1
0500
(ooo
ooo)
1
1
6
044401
WG,
020001 1 RG4
WG,
040002
1
(o2C
OOl)
0
000000'
RLI0B8
(ooo
500)
(OOO OOl)
A
020001 RSC<
(020
ooi) WSC
1 WA
,040002 ▼ 000001
WA
040002
L
044401
Q
(040
ooz)
Z
000500
(040
X)2) RZ
u
000022
RU
040002 RU
Y
000021 WY
'020001
X
000001 A2X • 020001
Cl
SO
020
TIME
1
2
3
4
5
6
7
8
9
10 II 12
STAGE
ERASABLE
TOV SETS
RBI PLACES
ST 2 SETS
RC AND
ERASABLE
COUNTER
MEMORY
C(BR)* 01
000001 ON
STAGE
TM2 SET
MEMORY
IS SET
STROBE IS
WRITE LINES
COUNTER
C(BR)*XI
STROBE IS
TO OOl
INHIBITED
TO 010
INHIBITED
BY ADDRESS
BY PREVIOUS ADDRESS
0000 IN S
0000 IN S
40716
Figure 4-35. Subinstruction DAS1, with Overflow and Implied Address Code
DDOUBL, Data Transfer Diagram
4-122
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
F M
EM
' 40000
1 40445
CH
S
1005
> WS 1005
(om
0C5)
G
021005
WGA 000000
140000 RG
' WG
100445
1
1
B
021005
RLIOBB J WB A 102000
RB* WB
001004
(oooooo) (102000)
M O2OO0) (OOI
004) (Too
445)
A
102000
WA 140444
RSC* RA* ♦— - 1
WA?
WSC
RAi
WA
101777
L
100444
RSC | RL *-(140444)
WL
1 001004
RL'
' WSC .
Q
(ooi
DOS) RSC |
([40
300) WSC
Z
000203
rsc 1 (ooi"
D04)
WSC «
(^2
OOO) (ToT
r
u
000203
RU'
1 001004
RU'
100445
RU'
101777
Y
000202 \
WYI2 001005 WY'
140000 WY1
102000
X
000000 • MONEX 177 776 A2X*I40444 M0NEX*I77776
Cl
1
SO
021
TIME
1
2 3
4
5
6
7
8 9
10 II
STAGE
COUNTER
IS SET
TO 000
Cl SETS
CARRY
FLIP-FLOP
RSC IS
INHIBITED
BY ADDRESS
1005 INS
TOV SETS
C(BR)= 10 -
WSC IS INHIBITED
BY ADDRESS
1005 IN S
STI SETS
STAGE COUNTER
TO OOI
40717
Figure 4-36. Subinstruction DASO, with Underflow, Data Transfer Diagram
4-123
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00300
CH
S
1005
, WS 1004
WS
,0203
(ooi
004)
6
100445
WG| OOOOOO
’000300 '
RG WG,
102277
1
1
B
001004
1 RLIOBB J
(oooooo)
(l02
177) (177776) ^00
203)
A
101777
RScj
WSC
WA? 177776
L
001004
RSC |
(000
300) WSC
WL« OOOOOO
Q
RScj
WSC
Z
000203
RSC •
WSC
RZ
u
101777
RU'
102277
Y
102000
WY
'000300
X
177776
A2X*I0I777
Cl
SO
021
TIME
2
3
4
5
6
7
8
9 10
II
12
STAGE
RSC IS
WSC IS
RIC PLACES
ST2
RC AND
COUNTER
INHIBITED
INHIBITED
177776 ON
SETS
TMZ SET
IS SET TO
BY ADDRESS
BY ADORESS
WRITE LINES
STAGE
C(BR)= XO
OOI
1004 IN S
1004 IN S-
COUNTER
TOV SETS
C(BR)*IO
TO 010
40718
Figure 4-37. Subinstruction DAS1, with Underflow, Data Transfer Diagram
4-124
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
1 33333
1 55555
CH
S
2300
WS 0300
WS
6000
(ooo
300)
G
022300
WG| 000000
033333
'RG WG
J 5 5555
155555
I
1
(l55
555) (006
000)
B
02230r .
RLIOBB | W8A 155555
RB <
155555
(goooog)
55S) (033
333) (J55555)
A
RSC |
WSC j
L
155555 RSC j RL'
'155555
WL 033333 WSC 1
0
RSC | wsc |
z
006000 RSC 1 WSC 1 RZ<
006000
u
006000
Y
005777
X
000000
Cl
'
SO
022
TIME 1 2 3 4 5 6 7 8 9 10 II 12
STAGE RSC IS WSC IS ST 2 SETS
COUNTER INHIBITED BY INHIBITED STAGE COUNTER
•S SET ADDRESS 0300 BY ADDRESS TO 010
TO 000 IN S 0300 IN S
Figure 4-38. Subinstruction LXCHO, Data Transfer Diagram
4-125
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
22222
22223
CH
S
4300
WS 0300
WS
1 6000
(ooo
300)
G
024300
WG ^ 000000 '
T022222
' RG WG
1 022223
022223
(oooooo)
0
024300 '
■ I
RLIOBB |
(022
223) (006
000)
i
A
i
RSCJ
WSC4
L
RSc| (022
222) WSC 1
Q
RScj
WSC 1
Z
006000 RSci
WSC
RZ «
006000
u
006000
RU 1
022223
Y
005777 WY'
022222
X
000006 WY • 000000 • PONEX 000001
Cl
1
SO
024
TIME
1 2 3
4
5
6
7
B
9
10
II
12
STAGE
COUNTER
IS SET
TO 000
RSC IS INHIBITED
BY ADDRESS
0300 IN S
TSGN,
TMZ.AND
TPZG ARE
NOT USED
BY INCRO
WOVR HAS
NO EFFECT
SINCE U
DOES NOT
CONTAIN
OVERFLOW
ST2 SETS
STAGE
COUNTER
TO 010
40720
Figure 4-39. Subinstruction INCRO, Data Transfer Diagram
4-126
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
i 00030
CH
S
6200
iWS 0200
WS
,0633
(poo
200)
G
026200
000000
000030
>RG WG
007530
1
1
_
B
026200 (
RUOBB J
($K30
633)
(ooooog)
(oooooo)
A
007500 RSC A
WSC
WAY 000000
WA,
,007530
L
RSC j (000
030) WSC i
Q
RSC |
WSC i
(007
530)
Z
000633 RSC 1
WSC
RZ (
•000633
(007
530)
u
000633
RU
1007530 RU<
007530
Y
000632 WY '
000030
X
000000 A2X« 007500
Cl
1 0
SO
026
TIME
1 2
3
4
5
6
7
8
9 10
STAGE
RSC IS
TOV IS
RBI.RIC
ST2 SETS
C(B) CAN NEVER
COUNTER
INHIBITED BY
NOT USED
AND WA
STAGE
BE 000000 FOR
IS SET
ADDRESS
BY ADSO -
ARE NOT
COUNTER
ADSO - THEREFORE
TO 000
0200 IN S
WSC IS
USED BY
TO 010
RC IS NOT USED
INHIBITED
ADSO BUT
BY ADSO AND TMZ
BY ADDRESS
STILL
RESETS BR2
0200 INS
CHANGE
CCA) AT
TIME 7
40721
Figure 4-40. Subinstruction ADSO, Data Transfer Diagram
4-127
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
144444
,44444
CH
S
0400
WS
,6000
G
030400 WG^ OOOOOO '
- 1 -
144444 RGf
WG A 1
>144444
044444)
- ~H~~ -
M44444)
B
030400 (OOOOOO) WB 144444? (006
TOO) RB* RB#I44444
1
- 1 -
(l44444)
A
RSCf
- -
WA'
144444
L
RSC*
|
Q
1
RSC+
- 1 - - -
Z
006000 RSC* RZi
U
006000
Y
005777
X
OOOOOO
Cl
1
SQ
030
8 9 10 II 12
ST2 SETS
STAGE
COUNTER
TO 010
TIME 12 3 4 5 6 7
STAGE RSC IS
COUNTER INHIBITED BY
IS SET ADDRESS
TO 000 0400 INS
40722
Figure 4-41. Subinstruction CAO, Data Transfer Diagram
4-128
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
t
1
EM
•25252 1
1
25252
CH
1
S
0300
ws,
I
6000
1
1
|
G
140300 WGfOOOOO
1
'025252 V RG#
WGA025252 i
(025252)
(025252)
8
WB i ^
140300 (OOOOOO) 025252? (006
ooo) RB^ RC4
• 152525
1
1
M52525)
A
1
rsc4
i
WA
'152525
L
- 1
RSC?
1
Q
1
RSC?
|
Z
1
006000 RSC« RZ<
>006000
U
006000
Y
005777
X
OOOOOO
Cl
1
SQ
010
TIME
1 2
3
4
5
6
7 S
STAGE
RSC IS
FIXED
ST2 SETS
COUNTER
INHIBITED BY
MEMORY
STAGE
IS SET
ADDRESS
STROBE IS
COUNTER
TO 000
0300 IN S
INHIBITEDBY
ADDRESS
0300 IN S
TO 010
40723
Figure 4-42. Subinstruction CSO, Data Transfer Diagram
4-129
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
u
000600
Y
000577
X
000000
Cl
'
SO
TIME
1 2
3
4
5
6 7
8 9 10 II 12
STAGE
RSC IS
TRSM
FIXED
STI SETS
COUNTER
INHIBITED
HAS NO
MEMORY
STAGE COUNTER
IS SET
BY ADDRESS
EFFECT
STROBE IS
TO 001
TO 000
0300 IN S
SINCE
INHIBITED BY
CISJIS
ADDRESS 0300
NOT
0017
(RSM
ADDRESS)
IN S
Figure 4-43. Subinstruction NDXO, Data Transfer Diagram
40724
4-130
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
I
EM
► 12156 1 1
|
12156
CH
i
1
S
0600
WS|
1
,3545
1
1
G
021367 WGAOOOOOO
012156 1 RG4
*012156
i
B
021367 (OOOOOO) RB4
> WB
J3777I
RB* WB
>033545 RB'
- — F— -
1
U3777j)
(033
545) (l3777l)
A
- 1 -
137771 RSC +
RAi
' WA,
,021367
WAf 137771
L
RSC+ (02^
367) (021"
367) (oi2
^56)
(033
545)
0
- 1 -
RSC+
z
000600 fRZ RScl WZ'
021367 RZ<
1 WZA00060I
(ooo
SCX}) (00060^)
(033
545)
u
000600
RU*00060I
RU*
033545 RU<
*033545
Y
000577
WYI2
000600 WY
1 012156
X
WYI2
000000*000000 A2X *021367
Cl
1 1
so
050 WSQ
’033
TIME
1
2
3
4
5
6
STAGE
Cl SETS
NISO
FIXED
COUNTER
CARRY
GENERATES
MEMORY
IS SET
FLIP-
RB AND
STROBE IS
TO 001
FLOP
WSO AT
INHIBITED
TIME 12
BY ADDRESS
RSC IS
INHIBITED
BYADORESS
0600 IN S
0600 IN S
40725
Figure 4-44. Subiustruction NDX1, Data Transfer Diagram
4-131
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
u
001064
Y
001063
X
000000
Cl
1
SO
050
TIME
1
2 3
4
5
6
7
8
9
10
II
12
STAGE
WSC IS
TRSM SETS
FIXED
STI SETS
COUNTER
INHIBITED
STAGE
MEMORY
BIT 1 OF
IS SET
BY ADDRESS
COUNTER
STROBE IS
STAGE
TO 000
0017 IN S
TO 010
INHIBITED
COUNTER
SINCE
BY ADDRESS
RESULTING
c (S) IS 0017
0017 IN S
IN Oil
Figure 4-45. Subinstruction NDXO, with Implied Address Code RESUME,
Data Transfer Diagram
40726
4-132
i
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
40727
Figure 4-46. Subinstruction RSM3, Data Transfer Diagram
4-133
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
.01726
.00006
CH
S
1064 A WS 0015
WS
1 1726
(000015)
G
000006 WG«000000 '
001726
iRG WG A 000006
000006
(000006)
B
000006
RB • WB
.001726 rb,
A
(OOI
726) <£»
726)
L
Q
Z
001064 vVZ 1
001726 RZ ( RAD) <
U
001064
Y
001063
X
000000
Cl
’
SO
050 150 WSQ '
100
TIME
1
2
STAGE
RI5
NISO
COUNTER
PLACES
CAUSES
IS SET
000015
RB AND WSQ
TO Oil
ON
AT TIME 12-
WRITE
RSC IS NOT
LINES
USED BY
RSM3
ST2 (RAO) SETS
STAGE COUNTER
TO OIO-EXTPLS
SETS BIT EXT
OF SO
40728
Figure 4-47. Subinstruction RSM3, with Implied Address Code EXTEND,
Data Transfer Diagram
4-134
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
34677
73660
CH
S
24 00
kWS 0400
WS
i 0377
(000
400)
6
052400
WG|000000 ’
034677
>RG WG
1 173660
173660
1
1
(l73
660)
B
052400
1 RLI08B J WB A 173660
RB i
WB
000377
(pooooo) (iTI
660) (034
57t) (r73660)
A
023615
R5C\
WSC f
L
173660
RScj RL
i WL'
034677 WSC '
(ooc
377)
Q
(poo
400) RSc| WScj
Z
001233
rscI wsc i
u
001233
RU <
000377
Y
001232 i
WYI2
000400
X
000000 «MONEX 177776
Cl
' '
SO
052
TIME
•
2 3
4
5
6
7
8
9
10 II
STAGE
Cl SETS
RSC IS
WSC IS
STI SETS
COUNTER
CARRY
INHIBITED
INHIBITED
STAGE COUNTER
IS SET
FLIP-
BY ADDRESS
BY ADORESS
TO 001
TO 000
FLOP
0400 INS
0400 IN S
40729
Figure 4-48. Subinstruction DXCHO, Data Transfer Diagram
4-135
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
1 21217
, 23615
CH
S
0377
> WS 0377
WS
1 1233
(ooc
377)
G
173660
WG^ OOOOOO '
021217
i RG WG
k0236l5
1 023615
1
1
(022
615) (ooi
8
000377 «
1
►RLIOBB 1 WB
023615 (027
217) RB<
023615
(OOOOOO) (023
6 15)
(023615)
A
023615 RSC J RA'
023615 WA'
021217 WSC1
L
034677 RSC j WSC '
0
RScj WSC I
Z
001233 RSci WSC 1 RZ<
001233
U
000377
Y
000400
X
177776
Cl
1
SO
052
TIME
STAGE
COUNTER
IS SET
TO 001
RSC IS
INHIBITED
BY ADDRESS
0377 INS
WSC IS
INHIBITED
BY ADDRESS
0377 INS
ST2 SETS
STAGE
COUNTER
TO 010
40730
Figure 4-49. Subinstruction DXCH1, Data Transfer Diagram
4-136
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
EM
'00411
1 70460
CH
S
4200 i
WS 0200
WS
1 2754
(£00
200;
G
054200
WG A 000000
000411 WG 4 170460
' 170460
(^70460)
B
054200 i
RLIOBB * WB 4 170460 RB •
I !
(000000) (£70460) (l70460) (002
754)
A
170460 RScj RA* | WSC
L
rsc| I WSC
0
RSC^ |wSC
z
002754 RSC 1 RZ '
WZ 4002754 I WSC RZ '
(002
754) (002754)
U
002754
RU *002754
Y
002753 WYI2'
002754
X
000000 WYI2*000000
Cl
1 0
SQ
054
TIME
2
3
4
5
6
7
8
9
10
II
12
STAGE
RSC IS
TOV SETS
WSC IS
ST2 SETS
COUNTER
INHIBITED
C(BR) = 00
INHIBITED
STAGE
IS SET
BY
BY
COUNTER
TO 000
ADDRESS
ADDRESS
TO 010
0200 INS
0200 IN S
40731
Figure 4-50. Subinstruction TSO, without Overflow or Underflow,
Data Transfer Diagram
4-137
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
1 00411
, 03511
CH
S
A 200
i WS 0200
WS
1 2755
(ooo
200)
G
054200
WG^OOOOOO
'000411 WGA0435II
1 043511
1
(0435ll)
B
0542001
RLIOBB i WB A 04 351 1 RbI
I I T
(oooooo) (oXaslT) (OOOOOl) (o43Sm) (q02
A
043511 RSC I RaI WAYOOOOOI j WSC
r
L
Rsc| jwsc
Q
RSC | jwSC
z
002754 RSC 1 RZ(
WZ A002755 ^WSC RZ'
(00275S)
u
002754 (002
75^) RU A 002755
Y
002753 WYI2 1
002754
X
OOOOOO WYI 2 *000000
Cl
1 1
SQ
TIME
1 2
3
4
5 6
7
8 9
STAGE
COUNTER
IS SET
TO 000
RSC IS
INHIBITED
BY
ADDRESS
0200 IN S
TOV SETS
C(BR)= 01
RBI PLACES
OOOOOl
ONTO WRITE
LINES
WSC IS
INHIBITED
BY ADDRESS
0200 IN S
ST2 SETS
STAGE COUNTER
TO 010
40732
Figure 4-51. Subinstruction TSO, with Overflow, Data Transfer Diagram
4-138
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
1 00411
,43220
CH
S
4200
IW 3 0200
WS
.2775
(000
200)
G
054200
WG^ 000000
1
000411 WG AI03220
'103220
I (K3322o)
1 H —
B
054200 <
1
1 RLI08B | WB AI03220 RB f
(000000) (l0322o) U77776) U0322o) (002
775)
A
103220 RSCf RA4 WA f 177776 1 WSC
1 1
L
1 1
RSC^ ♦ WSC
1 |
Q
1 1
RScf + WSC
Z
002754 RSci RZf WZA002755 ^WSC RZ'
(002
F54) (002755)
U
002754
RU*002755
Y
002753 WYI2'
002754
X
000000 WYI2 *000000
Cl
'
SO u54
TIME
2
3
4
5
6 7
8
STAGE
RSC IS
TOV SETS
RIC
WSC IS
ST2
COUNTER
INHIBITED
C(BR)= 10
PLACES
INHIBITED
SETS
IS SET
BY ADDRESS
177776
BY ADDRESS
STAGE
TO 000
0200 IN S
ON
0200 IN S
COUNTER
WRITE
TO 010
LINES
40733
Figure 4-52. Subinstruction TSO, with Underflow, Data Transfer Diagram
4-139
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
i23336
, 66345
CH
S
0430
,WS 0430
WS
,1744
(600
430)
G
056430
WG| 000000
023336 1
iRG WG
,066345
i066345
1
1
(066
345)
B
056430 1
RLIOBB j WB A 066345 (023
336) RB1
(ocn
744)
(600000) (066345)
(066345)
A
066345 RSC f RA • WA ’
023336 WSC '
L
RSC I WSC'
Q
RSC | WSC '
Z
001744 RSC 1 WSC ^ RZ'
U
001744
Y
001743
X
000000
Cl
•
SQ
056
TIME I 2 3 4 5 6 7
10 II 12
STAGE RSC IS
COUNTER INHIBITED
IS SET BY ADDRESS
TO 000 0430 IN S
WSC IS ST2 SETS
INHIBITED STAGE COUNTER
BY ADDRESS TO 010
0430 IN S
40734
Figure 4-53. Subinstruction XCHO, Data Transfer Diagram
4-140
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
25252 1
25252
CH
1
1
S
1213
1
, WS(
0660
1
1
G
0601213 WG 1 000000
025252 1 RG •
WGA025252 1
' 025252
(025252)
i
(025252)
8
0601213 (OOOOO^) WB f 025252
RB • RB <
025252
! <?°°
660)
A
000102 RSC |
WA ,
025354
L
RSC I
Q
RSC I
(025
252) (025
354)
Z
000660 RSC 1 RZ<
1 000660
U
000660
RU
>025354
Y
000657 WY
025252
X
000000 A2X • 000102
Cl
1 0
SO
060
TIME 12 3 4
STAGE RSC IS
COUNTER INHIBITED
IS SET BY ADDRESS
TO 000 1213 IN S
FIXED
MEMORY
STROBE IS
INHIBITED
BY ADDRESS
1213 IN S
ST2 SETS
STAGE
COUNTER
TO 010
407J5
Figure 4-54. Subinstruction ADO, Data Transfer Diagram
4-141
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
i 33215 .
33215
CH
1
1
S
0100
WS
1232
1
1
6
070100 WG^ 000000
033215 I RG •
' 033215
(033215)
B
070100 (000000) WBA000222 <
RC 177555 WBf 033215
RC
144562
iWBI77577 • RC 000200
(000222) (177555) (ooi"
f32^
IOOO2O0)
A
000222 RSCJ Ra! WA'
177555
RA<
1 177555
WA’ 000200
L
RScj
0
RSC |
r
z
001232 RSC 1 RZ 1
^77
U
001232
RU'
1 177577
Y
001231 RU 1
177577
X
000000 WY«000000
Cl
1 0
SO
070
TIME
1 2
3
4
5
6
7
8
9 10
II
STAGE
RSC IS
FIXED
ST2 SETS
COUNTER
INHIBITED
MEMORY
STAGE COUNTER
IS SET
BY ADDRESS
STROBE IS
TO 010
TO 000
0100 IN S
INHIBITED
BY ADDRESS
MASK (AND) OPERATION
0100 IN S
b (0100) =
0 0 1 1 0 1 1 010 OOI
101
b (A ) •
0 000 000 010 010
010
c (A)
0 000 000 010 000
000
407*
Figure 4-55. Subinstruction MSKO, Data Transfer Diagram
4-142
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
023216 RCH
S
0013
lWS 000013
WS
1333
(00c
>013)
6
000013
(023
B
000013 -
'RLIOBB AWB 033412 WB1
023216 |RB WB 4023216 (OO^
333)
(033412) (023216) (023216)
A
033412 RaI WAf 023216 • RA
L
Q
Z
001333 RZ<
001333
u
001333
Y
001332 WY4000000
X
000000 WY4000000
Cl
1
SO
100
TIME 1 2 3 4 5 6 7 0 9 10 II 12
STACE ST2 SETS
COUNTER STAGE
IS SET COUNTER
TO 000 TO 010
40737
Figure 4-56. Subinstruction READO, Data Transfer Diagram
4-143
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
001006 RCH
» WCH
,111336
S
0014
i WS 0014
WS
i 1064
(ooc
014)
G
001014
WG
,111336 (001
006) (m
336)
B
001020 i
• RLIOBB i
WB II 1336 WB'
^001006
WBAIII336 (OO^
36 4)
Ml 12
136)
Ml 1336)
A
III 336 RA<
RJ
ra!
L
Q
Z
301064 R2'
001064
U
001064
Y
001063 WY • 000000
X
000000 WY • 000000
Cl
1
SO
101
TIME 1
2
3
4
5
6
7
8 9
STAGE
COUNTER
IS SET TO
000
WY
ST2 SETS
STAGE COUNTER
TO 010
40738
Figure 4-57. Subinstruction WRITEO, Data Transfer Diagram
4-144
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
40739
Figure 4-58. Submstruction RANDO, Data Transfer Diagram
4-145
LEM PRIMARY GUIDANCE, NAVIGATION, AND (ONTIOL SYSTEM
HD-1021042
MANUAL
FM
EM
CH
034211 RCH i
1 WCH |
020200
S
3015 ,
,WS 1015
WS,
1012
(00 1
015)
(020
200)
G
003015
(03<
r
B
003015 i
RUOBB '
RC ,
056577
WB RC .WB
034211 T 143566 tl57577 '
RC
020200
M2I200)
(157577) (157577) (020
200) (00T
)I2)
A
121200 RaI
WA<
157577 ArA WA'
020200
L
Q
(056
577) (l57
Z
001012
r
RZ 1
u
001012
RU'
056577
Y
OOIOII WY
056577
X
000000 WY« 000000
Cl
1 0
SO 103
TIME I <
STAGE SIO IS NOT
COUNTER DECOOED FOR
IS SET
TO 000
CHANNEL
INSTRUCTIONS
RC AND RU
PLACE
157577
ON WRITE
LINES
7 8 9
ST 2 SETS
STAGE
COUNTER
TO 010
40740
Figure 4-59. Subinstruction WANDO, Data Transfer Diagram
4-146
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
SO
104
TIME
1
2 3
4 5 6
7 8 9 10 II
12
STAGE
COUNTER
IS SET
TO 000
RB AND RU
PLACE 107773
ON WRITE LINES
ST2 SETS
STAGE COUNTER
TO 010
Figure 4-60.
Subinstruction RORO,
Data Transfer Diagram
40741
4-147
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
OOOIOI RCH
1 WCH
>022303
S
5014
,W5 1014
WS
, 1033
(ooi
014 )
(022
303)
6
005014
(ooc
101)
B
005014
'RLIOBB AWB 0223034
>RB WB'
OOOIOI
>RB WB A022303 (OO^
033)
(022303)
(022
303) (022303)
A
022303 RA*
WA 1
022303
L
1
0
(022
303) (022
303)
z
001033
RZ(
u
001033
RU <
022303
Y
001032 WY 1
022303
X
000000 WY *000000
Cl
1 0
SO
105
TIME
STAGE
COUNTER
IS SET
TO 000
1 2 3
SIO IS
NOT OECOOEO
FOR CHANNEL
INSTRUCTIONS
4 5 6
R8 AND RU
PLACE 022303
ON WRITE LINES
7 8 9 10
ST2 SETS
STAGE COUNTER
TO 010
II 12
Figure 4-61.
Subinstruction WORO,
Data Transfer Diagram
40742
4-148
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
SO
106
TIME 12 3 4 5
STAGE
COUNTER
IS SET
TO 000
RCH AND RC
PLACE
166535
ON WRITE
LINES
RA AND RC
PLACE
177777
ON WRITE
LINES
7 8 9 10 II 12
ST2 SETS
STAGE COUNTER
TO 010
EXCLUSIVE OR OPERATION
b (CH)» 0 000 000 001 000 100
blA)= 0 001 001 011 100 1 10
c ( A ) 1 0 001 001 010 100 010
40743
Figure 4-62. Subinstruction RXORO, Data Transfer Diagram
4-149
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
17321
01034
CH
S
7433 AWS00I5
(000015)
G
017433 WG • 000000
017321 WG<
,001034 i
> 001034
B
017433
(ooi"
334)
A
L
Q
Z
001034 R 2 4
U
001034
Y
001033
X
000000
Cl
1
SQ
107 1
TIME 1 2 3 4 5 6 7 8 9 10 II 12
STAGE RI5 PLACES RSC IS
COUNTER OOOOI5 ON NOT USED
IS SET WRITE BY RUPTO
TO 000 LINES
ST I SETS
STAGE COUNTER
TO 001
40744
Figure 4-63. Subinstruction RUPTO, Data Transfer Diagram
4-150
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
65201
,017433
CH
S
0015 AWS00I7
WS
, 04004
(000017)
G
001034 WG 000000 '
165201
WG 4017433
'017433
(017433)
B
017433 (04C
”04) rb!
A
L
0
z
001034 WZ A 04004 RZ «
U
001034
Y
001033
X
000000
Cl
'
SQ
107
•
TIME
1 2
3 4
5
6
7
8
9
10
II
12
STAGE
RI5 RSCIS
RRPA
ST2
KRPT
COUNTER
PLACES NOT
PLACES
SETS
REMOVES
IS SET
000015 USED BY
RUPT
STAGE
RUPT
TO 001
ON WRITE RUPT 1
ADDRESS
COUNTER
ADDRESS
LINES -
ON WRITE
TO 010
RB2
PLACES
000002 ON
WRITE LINES
LINES
40745
Figure 4-64. Sub instruction RUPT1, Data Transfer Diagram
4-151
LEM PRIMARY 6UIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
S
0200
G 010200
SO
110
TIME
1
2
3 4
5
6
7
8
9
10
II
STAGE
TSGN ANO
TMZ
RY ANO
COUNTER
TMZ SET
SETS
WB ARE
IS SET
C (BR) * 00
C(BR)=XO-
NOT USED
TO 000
OVST
BUT STILL
SETS
CHANGE
STAGE
C(B )-
COUNTER
TO 001
STAGE
40746
Figure 4-65. Subinstruction DVO, Data Transfer Diagram
4-152
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
• 21212 i
21212
CH
S
0200
G
010200
' 021212 RGf '
021212 L2GD *056000 '
RG
(021212)
B
010200
WB
i 033400 '
'RB WB ?02I2I2 RBj WB<
,165432 RB'
WB 174276,
(033
400)
(021212)
(056
OOl)
A
165432
|rSC RAi
WAT02I2I2
L
033400
' RL
WL ,
,073400 |RSC
RL ‘
173400
WL
167000
WL
'056001
0
(033
Too)
|rsc .
(l65
432)
(j74
276)
z
006135
(073
400) IrSC (|65
432)
(l67
)00) (l65
432)
400)
u
006135
RU '
073400
RU
'165432
RU
167000
174276 RU 174276
Y
006134 WYl
033400 WY
’165432 WYD
'167000 WYD
’153064
X
000000 BI5X • 040000 WY *000000 WYD«000000 A2X •021212
Cl
10 0 0 0
SO
110
TIME
4
5
6
7 8
9
10 II
12
1
2 3
STAGE
TOV SETS
RSC IS
PIFL
TSGU SETS STAGE
COUNTER
CIBR) =01
INHIBITED
FINDS
C(BR) = IX AND
IS SET TO
BY ADDRESS
LIS • 1
CAUSES RBIF-
001
0200 IN S -
RBlF PLACES
TSGN SETS
000001 ON
C(BR) = OX
WRITE LINES -
DVST SETS
STAGE COUNTER
TO Oil
40747
Figure 4-66. Subinstruction DV1, Data Transfer Diagram
4-153
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
S
0200
6
L2GD
056000 #034002 i
' RG L2GD* 070004 <
1 RG L2GD* 060010 1
1 RG L2GD *040022 '
1 RG
B
174276 '
► RB
WB i
170574 '
' RB
WB
.161371 i
1 RB
WB
.164174 1
' RB
171602 4
. WB
(034
002)
(070
om)
(06C
(040
023)
A
021212
• L
056001
WL 1
034002
WL
070004
WL
'060011
WL
040023
0
(r74
276) (|70
574) (|70
i74)
37?) (?6^
37?) (?64
7?) (^64
17?) (^7?
50?)
z
006135
u
174276
012007 RU<
' 170574
002604 RU <
1 16 1371
164174 RU.
.164174
171602 171602 4
1 RU
Y
153064 1
WYD
170574 WYD
1 161371 WYD'
142762 WYD
150370
X
A2X CLXC CLXC
021212 • 021212 *000000 A2X *021212 *000000 A2X • 021212 A2X • 021212
Cl
0 0 0 0 0
SO
no
TIME
4
5
6 7
8 9
10
II 12
1
2 3
STAGE
PIFL
TSGU
PIFL
TSGU
PIFL
TSGU SETS
PIFL
TSGU SETS STAGE
COUNTER
FINDS
SETS
FINDS
SETS
FINDS
C(BR) • IX
FINDS
C ( BR) ■ IX AND
IS SET
LI5 * 1
C(8R) S0X
LI5 *0
C(BR) ■ OX
LI5 * 1
AND CAUSES
LIS - 1
CAUSES RBI-
TO 01
AND
AND
RBI - RBI
RBI PLACES
CAUSES
CAUSES
PLACES
000001 ONTO
CLXC
CLXC
000001
WRITE LINES
ONTO
OVST SETS
WRITE
STAGE COUNTER
LINES
TO III
40748
Figure 4-67. Subinstruction DV3, Data Transfer Diagram
4-154
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
S
0200
G
040022 • 000046
IRG L2GD *000114
' L2G0*000232
IRG L2GD*000464
iRG
8
171602
• RB
WB
1163404
•RB
WB
il70223
'RB
WB
160447
•RB
WB 162331
(ooc
046)
(ooc
(000
(000
465)
A
021212
r
r
L
040023
WL'
000046
WL'
000115
WL'
000232
WL'
000465
0
(^Tt7
502) (l63
4W) <£T
404) (|70
223) (l70
223) (l6o'
447) (^60
447) (l62
33M
z
006135
u
171602
004617 RU(
>163404
170223 RU<
>170223
001662 RUi
160447
162331 RU 162331 1
r
150370 '
WYD 163404 WYD'
14701 1 WYD'
>160447 WYD'
1 4 1 1 17
X
A2X
021212 *021212 *CLXC 000000 A2X*02I2I2 A2X*02I2I2 *CLXC000000 A2X»02I2I2
CI
0
SO
110
TIME
4
5 6
7
8 9
10
II
12
|
2 3
STAGE
PIFL
TSGU
PIFL
TSGU
PIFL
TSGU
PIFL
TSGU STAGE
COUNTER
FINDS
SETS
FINDS
SETS
FINDS
SETS
FINDS
SETS
IS SET
LI5= 1
C(BR) = OX
LI5 = 0
C ( BR ) = IX
LI5 =0
C(8R)=0X
LI5 = 0
CIBR): IX
TO II
AND CAUSES
AND CAUSES
AND CAUSES
AND CAUSES
CLXC
RBIF -
CLXC
RBIF-RBIF
RBIF PLACES
PLACES
000001
000001 ONTO
ONTO WRITE
WRITE LINES -
LINES
DVST SETS STAGE
COUNTER TO 110
40749
Figure 4-68. Subinstruction DV7, Data Transfer Diagram
4-155
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
S
0200
6
L2GD
000464*001152 '
iRG L2GD» 002326 '
iRG L2GD *004656 1
RG L2GD *011534 1
»RG
B
162331 i
»RB
WB,
, 166075 1
RB
WB 1
175405 1
1 RB
WB ,
,173013 (
1 RB
WB
166027,
(ooT
5?)
(002
(004
656)
(00?
A
021212
r
L
000465
WLl
001153
WLl
002327
WL
'004656
WL
'011534
0
(162
33?) (166
D75) (166^
375) (175"
405) (l73
013) (l73
0?3) (?66
027) (j66”
>27)
z
006135
u
162331
166075 RU
* 166075
175405 RIM
• 175405
014226 RU 1
1 173013
RU
007242 166027
r
141 1 17
WYD
' 144663 WYD
' 154173 WYOl
'173013 WYD
' 166027
X
A2X CLXC CLXC
021212 • 021212 A2X *021212 A2X *021212 *000000 A2X *021212 *000000
CI
0
so
110
TIME
4
5 6
7
8 9
10
II 12
1
2
3
STAGE
PIFL
TSGU SETS
PIFL
TSGU SETS
PIFL
TSGU SETS
PIFL
TSGU SETS
STAGE
COUNTER
FINDS
C(BR) = IX
FINDS
C(BR)* IX
FINDS
C(BR) *0X
FINDS
C(BR)=OX
IS SET
TO MO
LI 5*0
AND CAUSES
RBIF-RBI F
PLACES
000001
ON WRITE
LINES
LI5» 0
AND CAUSES
RBIF-RBIF
PLACES
000001
ON WRITE
LINES
L 1 5 * 0
AND CAUSES
CLXC
LI 5 = 0
AND CAUSES
CLXC-DVST
SETS STAGE
COUNTER
TO 110
40750
Figure 4-69. Subinstruction DV6, Data Transfer Diagram
4-156
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
S
0200 WS,
>6135
6
011534 L2GD* 023270 • RG
(oz:
27l)
B
166027 RB«
WB'
023271
W84
175271 (
RC
*002506
(006
”l35)
A
021212
WA '
023271
(002
506)
L
011534
WL
>175271
WL
P002506
Q
^66
027)
Z
006135
RZ
r
u
166027
175271 RU<
*175271
Y
166027 WYDl
'154057
X
000000 A2X»02I2I2
Cl
0
SQ
no
TIME 1
2
3
4
5
6
7 8
STAGE
PIFL
TSGU
RZ AND
ST2 AND RSTSTG
COUNTER
FINDS
SETS
TOV SET
SET STAGE
IS SET
LI 5*0
C(BR) = IX
C(BR)=00
COUNTER
TO 100
AND CAUSES
AND CAUSE
TO 010-
RBIF-RBIF
NO ACTION
TSGN SETS
PLACES
AT TIME 7
C(BR)*OX
000001
AND CAUSES
ON
RC AND WL
WRITE LINES
AT TIME 10
407 SI
Figure 4-70. Subinstructiou DV4, Data Transfer Diagram
4-157
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
u
000437
Y
000436
X
000000
Cl
'
SO H6
TIME
1 2
3
4
5
6
7
8
9
10
II
12
STAGE
COUNTER
IS SET
TO 000
RSC IS
INHIBITED
BY ADDRESS
6055 IN S
TSGN
AND TMZ
ARE NOT
USED
BY BZFO
TPZG
SETS
C(BR)»XO
ST2 SETS
STAGE
COUNTER
TO 010
40752
Figure 4-71. Subinstruction BZFO, with Branch on Non-Zero Quantity,
Data Transfer Diagram
4-158
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
> 20221
EM
CH
S
6055
WS ,
,0221
(020
22N
G
016055 WG 000000 WG^
,000000
020221 RAO
(02022l)
B
016055 (OOO
000) RB(
WB
'020221 RB
A
000000 RA
L
0
(016
055)
z
000437
WZ
, 006056
(006056 ) (020
22N
u
000437
RIM
,006056
Y
000436 WYI2 '
006055
X
000000 W Y 1 2 *000000
Cl
1 1
SO
116 WSO'
r020
TIME
1 2
3
4
5 6
7
8
STAGE
RSC IS
TSGN
TPZG
Cl SETS
NISO
COUNTER
INHIBITED
AND
SETS
CARRY
CAUSES
IS SET
TO 000
BYADORESS
6055 IN S
TMZ
ARE
NOT
USED
BY
BZFO
CIBRl'-XI
FLIP-FLOP
RB AND
WSQ AT
TIME 12
40753
Figure 4-72. Subinstruction BZFO, with Branch on Plus Zero,
Data Transfer Diagram
4-159
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
00006
EM
CH
S
2160
WSi
,1200
G
012160 WG*000000 WG
i 003210
'000006
B
012160 (003
210)
A
003210 RA
i (ooi"
200)
L
0
z
001200 RZ
'(RAO)
U
001200
Y
001177
X
000000
Cl
.
SO
112 M2
TIME
1 2
3
4
5
6
7
8
STAGE
COUNTER
IS SET TO
000
RSC IS
NOT USED
BY
BZMFO
TSGN
ANO
TMZ
ARE
NOT
USED
BY
BZFO
TPZG
SETS
C(BR)--XO
EXTPLS SETS
BIT EXT OF SQ-
ST2 SETS
STAGE COUNTER
TO 010
40754
Figure 4-73. Subinstruction BZFO with Implied Address Code EXTEND,
Data Transfer Diagram
4-160
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00032
,00032
CH
S
0500
i WS0500
WS,
1330
(000
50 o)
G
020500
WG|000000 '
000032 | RG
WGA000032
000032
(000032) (o£
330) (000032)
B
020500 1
I T
RLIOBB | WB V 000032 ,
RC 177745
RB i
(00000^
A
004444 RSC 4
WA ,
004412
WA
,004412
L
RSC +
Q
RScj (l77
745) (00<
(004
412)
Z
1
001330 RSC*
r
RZ«
u
001330
RUS<
004412 RUS1
Y
001327 WYt
177745
X
000000 A2X«004444
Cl
1 *
SQ
120
TIME
1 2
3
4
5
6
7
8
STAGE
RSC IS
Cl SETS
TSGN
ST2 SETS
COUNTER
INHIBITED
CARRY
SETS
STAGE
IS SET
BY ADDRESS
FLIP-
C(BR)*OX
COUNTER
TO 000
0500 IN
FLOP
AND
TO 010
S CAUSES
NO ACTION
AT TIME
10
10 II 12
40755
Figure 4-74. Subinstruction MSUO with Positive Resultant, Data Transfer Diagram
4-161
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
» 43317
i 43317
CH
S
0500
WS 0500
WS
1 1330
(ooc
500)
G
020500
WG^OOOOOO '
PI433I7 fRG
WG *143317
143317
| Q433I7)
- 1 - I
(l 4 3 317)
B
020500 1
i RLIOBB | WB ? 143317
RC 034460 (ooi"
330) RbI
(000000)
A
020321 RSC^
WA
155002
RA
i WA
L
RSci
0
RSc| (034
460) (j55"
302)
OOl)
Z
001330 RSci
RZ<
(isT
)02)
u
001330
RUS<
055002
RUS»
155001
Y
001327 WY i
034460 WY 1
155002
X
000000 A2X* 020500 MONEX •177776
Cl
1 1
SO
120
TIME
1 2
3
4
5
6
7
8
9
10
II
12
STAGE
COUNTER
IS SET
TO 000
RSC IS
INHIBITED
BY ADDRESS
0500 IN S
Cl SETS
CARRY
FLIP-
FLOP
TSGN
SETS
C(BR)*IX
ST2 SETS
STAGE
COUNTER
TO 010
407S6
Figure 4-75. Sub instruction MSUO with Negative Resultant, Data Transfer Diagram
4-162
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
177777
i325oA
CH
S
2204 WS
,0204
WS
1057
G
022204
WG^ 000000 1
177777 RG<
1 WGA032337
>032337
(ooo
i
(032337')
B
022204 i
- 1
•RLIOBB | WB
032337
rb| (ooi
>57)
(ooo ooo)
777) (032337)
A
RSC| (f)32
337)
wscf
1
L
RSci
wscf
0
1
032337 RSC^ RO'
1 wo1
1
177777 WScf
z
1 1
001057 RSci WSci RZ<
U
001057
Y
001056
X
000000
Cl
■
SO
122
TIME
STAGE
COUNTER
IS SET
TO 000
2
RSC IS
INHIBITED
BY ADDRESS
0204 IN S
3 4
5
6 7 0 9
WSC IS ST2
INHIBITED SETS
BY ADDRESS STAGE
0204 IN S COUNTER
TO 010
10
II
12
407S7
Figure 4-76. Subinstruction QXCHO, Data Transfer Diagram
4-163
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
03266
,03267
CH
S
4100
WS 0100
WS
>001665
(ooc
ioo)
G
024100
WGjOOOOOO '
003266
|RG WG<
,003267
i
'003267
1
1
B
024100
1 RLIOBB J
(ooooo^
($>03
267) (oOl"
665)
A
RSC |
WSC
L
RSC | (003
266) WSC
0
RSC |
WSC
z
001665 RSC i
WSC
RZ<
u
001665
RU <
003267
Y
001664 WY'
003266
X
000000 WY« 000000 PONEX«OOOOOI
Cl
1 o
SO
124
TIME
2
3
4
5
6
7
8 9 10
II
12
STAGE
RSC IS
TSGN SETS
WSC IS
ST2 SETS
COUNTER
INHIBITED
CIBRI’OX-
INHIBITED
STAGE
IS SET
BY ADDRESS
TMZ AND
BY ADDRESS
COUNTER
TO 000
0100 IN S
TPZG ARE
0100 INS-
TO 010
NOT USED
WOVR DOES
BY AUGO
NOT CAUSE
AN INTERRUPT SINCE NEITHER
OVERFLOW NOR
UNDERFLOW OCCURRED
407S8
Figure 4-77. Subinstruction AUGO with Positive Quantity, Data Transfer Diagram
4-164
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
» 77203
77202
CH
S
4100
iWS 0100
WS
> 1665
(oooioo)
G
024100
WG | OOOOOO
177203
1 RG WG
, 177202
' 177202
1
1
B
024100 '
' RLI08B 1
(oooooo)
€
202)
i65)
A
RSC 4
wsc
L
1 /
RSC J (177
203) wsc ^
Q
RSC J
wsc
Z
001665 RScl
wsc
RZ 1
u
001665
RU 1
• 177202
Y
001664 WY 1
177203 MONEX* 177776
X
OOOOOO WY • OOOOOO
Cl
1 0
SO
TIME
1 2
3
4 5
6 7
8
STAGE
RSC IS
TSGN SETS
WSC IS INHIBITED
ST2
COUNTER
INHIBITED
C(BR) = IX-
BY ADDRESS
SETS
IS SET
BY ADDRESS
TMZ AND
0100 INS - WOVR
STAGE
TO 000
0100 IN S
TPZG ARE
DOES NOT CAUSE
COUNTER
NOT USED
AN INTERRUPT
TO 010
BY AUGO
SINCE NEITHER
OVERFLOW NOR
UNDERFLOW
OCCURRED
40759
Figure 4-78. Sub instruction AUGO with Negative Quantity, Data Transfer Diagram
4-165
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
F M
EM
03266
,03265
CH
S
GIOO
|WS 0100
WS
,1665
(ooo
100)
G
026100
WG^ 000000
003266
iRG WG
,003265
*003265
1
1
B
026100
< RLIOBB J
^OO^O)
(003
266) (oo7
565)
A
RSC |
WSC
L
RSC I (003
266) WSC
0
RSC |
WSC
z
001665 RSC 1
WSC i
RZi
u
001665
Y
001664 WY '
003266 RU <
003265
X
000000 WY • 000000 MONEX* 177776
Cl
1 0
SO
126
TIME
2
3
4
5
6
7 8 9 10
II
12
STAGE
RSC IS
TSGN SETS
WSC IS ST2
COUNTER
INHIBITED
C(BR) = OX-
INHIBITED SETS
IS SET
TO 000
BY ADDRESS
0100 IN S
TMZ AND
TPZG ARE
BY ADDRESS STAGE COUNTER TO 010
0100 IN S-
NOT USED
WOVR DOES NOT
BY DIMO
CAUSE AN INTERRUPT
SINCE NEITHER OVERFLOW
NOR UNDERFLOW OCCURRED
40760
Figure 4-79. Subinstruction DIMO with Positive Quantity, Data Transfer Diagram
4-166
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
> 77203
,77204
CH
S
6100
iWS 0100
WS
1 1665
(OOC
100)
G
026100
WG ^ 000000
177203
'RG WG
J77204
1 177204
1
1
B
026100 <
► RLI0B8
<6oOOOO)
(l 77
204) (001
565 )
A
RSC#
WSC
L
RSC A (l77
203 > WSC
Q
RSci
WSC .
Z
001665 RSC •
WSC 1
RZ<
u
001665
RU«
177204
Y
001664 WY'
177203
X
000000 WY« 000000 PONEX* 000001
Cl
1 0
SO
126
TIME
2
3
4
5
6
7 8 9
10
II
12
STAGE
COUNTER
IS SET TO
000
RSC IS
INHIBITED
BY ADDRESS
0100 IN S
TSGN SETS
C(BR)* IX -
TMZ AND
TPZG ARE
WSC IS ST2 SETS
INHIBITED STAGE COUNTER
BY ADDRESS TO 010
0100 INS-
NOT USED
WOVR DOES NOT
BY DIMO
CAUSE AN INTERRUPT
SINCE NEITHER OVERFLOW
NOR UNDERFLOW OCCURRED
J07M
Figure 4-80. Subinstruction DIMO with Negative Quantity, Data Transfer Diagram
4-167
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
1
'11231 |
>11231
CH
1
1
S
0133
| WS,
,0132
1
1
|
G
030133 WG f 000000
011231 ^ RG»
WGAOII23I 1
>011231
j (^011230
^OII23M
8
030133 1
>RB (^OOOOO) Wb1oH23I
Rsi RBI
jg
132)
A
t
RScj
("oi
23l)
L
1
RScj
WL
'011231
Q
(03C
133) RScj
Z
000103
rscA
u
000103
RU>
•000132
Y
000102
1 WYI2 000133
X
000000 MONEX 177776
Cl
1 1
SQ
130
TIME I 2 3 4 5 6 7 8 9 10 II 12
STAGE
Cl SETS
RSC IS
FIXED
STI SETS
COUNTER
CARRY
INHIBITED
MEMORY
STAGE
ISSET
FLIP-
BY ADDRESS
STROBE IS
COUNTER
TO 000
FLOP
0133 IN S
INHIBITED
TO 001
BY ADDRESS
0133 IN S
<0762
Figure 4-81. Subinstruction DCAO, Data Transfer Diagram
4-168
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
>33461 |
1
k 33461
CH
1
1
S
0132
WS
1 0103
1
1
G
OII23I WG^OOOOOO
- 1 -
033461 ♦ RG*
WG
>033461 '
'033461
| (03346?)
(03346l)
8
01 1231 (pooooo) WB
033461
RB<
RB»
€
?03)
(03346?)
A
1
RScf
- 1
WA<
033461
L
1
RSC^
1
0
RSC+
L
2
000103 RSC±
RZi
U
000132
Y
000133
X
177776
Cl
•
SQ
130
TIME 1 2 3 4 5 6 7
STAGE RSC IS FIXED
COUNTER INHIBITED MEMORY
IS SET BY ADDRESS STROBE IS
TO 001 0132 IN S INHIBITED
BY ADDRESS
0132 IN S
8
ST2 SETS
STAGE
COUNTER
TO 010
10 II 12
40763
Figure 4-82. Subinstruction DC Al, Data Transfer Diagram
4-169
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
• 51052
i 5I0S2
CH
S
0164
WS
,0163
G
140164 WG^OOOOOO
151052 RG«
WG A 151052 i
• 151052
M5I0521
M5I052)
B
140164
R8 (OOOOOO) WB 1 151052
rb! RCi
• 026725
163)
A
RSC+
1
(o2672s)
L
RSC|
j
WL'
026725
Q
(ho
164) RSC+
|
Z
000234
RSC 4
u
000234
RU'
000163
Y
000233 '
TWYI2 000164
X
0O00004M0NEX 177776
Cl
■ '
SO
140
TIME I
STAGE Cl SETS
COUNTER THE
IS SET CARRY
TO 000 FLIP-
FLOP
2 3 4 5 6
RSC IS
INHIBITED
BY AOORESS
0164 INS
7 8 9 10 II 12
ST I SETS
STAGE
COUNTER
TO 001
Figure 4-83. Subinstruction DSC 0, Data Transfer Diagram
4-170
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
34414
1 34414
CH
1
1
S
0163
WS
,0234
1
1
G
151052 WG^ 000000
034414 ^ RG •
WG A 034414
> 034414
(034414)
(634414')
B
151052 (60OOOO) WB ?0344I4
R8 • RC<
143363
(c™
2^) (l43363)
A
RSC i
WA '
143363
L
RSC j
0
RSC j
z
000234 RSC • RZ.
U
000163
Y
000164
X
177776
Cl
1
so
140
TIME
1 2
3
4
5
6
7
8
STAGE
COUNTER
IS SET TO
001
RSC IS
INHIBITED
BY ADDRESS
0163 IN S
FIXED
MEMORY
STROBE
IS INHIBITED
BY ADDRESS
0163 IN S
ST2 SETS
STAGE COUNTER
TO 010
40765
Figure 4-84. Sub instruction DCS1, Data Transfer Diagram
4-171
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
F M
T
EM
» 20011 j
>20011
CH
1
1
S
0134
1
1 ws
,1567
1
1
1
G
150134 WG| 000000
020011 j RG •
WG A0200II •
020011
(020oi?)
(0200IM
B
150134 (ooooo^ wb!o2ooii
rb!
1 (ooT
567)
A
RSC ♦
L
RSC f
1
Q
RSC j
1
Z
001567 RSC 1 RZ.
u
001567
Y
001566
X
000000
Cl
'
so
150
TIME 1 2 3 4 5 6 7 8 9 10 II 12
STAGE RSC IS FIXEO STI SETS
COUNTER INHIBITED BY MEMORY STAGE COUNTER
IS SET ADDRESS 0134 STROBE TO 010
T0 000 IN S IS INHIBITED
BY ADDRESS
0163 IN S
40766
Figure 4-85. Sub instruction NDXXO, Data Transfer Diagram
4-172
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
1
100333 -
>00333
CH
1
1
S
1567
ws
>0344
1
1
G
020011 WG|000000
000333 ♦ RG
'000333
•000333
1
1
B
020011 (QOOOOO) R8
• WB,
053216
RB*0532I6 ,
WB
,020344 RB
►
1
|
(053216)
(020
344) (053216)
A
053216 RSCf
j
RA<
' W A A 02001 1
WAV 053216
L
RSC+ (02C
on) (02C
On) (OOO
333)
(020
344)
Q
RSCf
Z
001567 *RZ RSC4 WZ
02001 1 RZ<
' WZA00I570
(oo
567) (001570)
(020
344)
u
001567
RU *001570
RUi
►020344 RUI
Y
001566 '
WYI2
001567 WY<
000333
X
WYI2
000000*000000 A2X*0200II
Cl
'
so
150 EXT IXX WSQ'
120
TIME
1
2
STAGE
Cl
NISO
COUNTER
SETS
GENERATES RB
IS SET
CARRY
AND WSO AT
TO 000
FLIP-
TIME 12 -
FLOP
RSC IS
INHIBITED BY
ADDRESS 1567
IN S
6
FIXED
MEMORY
STROBE
IS INHIBITED
BY ADDRESS
1567 IN S
9 10 II
EXT SETS
EXTEND FLIP-
FLOP OF SO
40767
Figure 4-86. Subinstruction NDXX1, Data Transfer Diagram
4-173
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
SO
160
TIME
1 2
3
4
5
6
7
8 «
STAGE
RSC IS
FIXED
ST2 SETS
COUNTER
INHIBITED
MEMORY
STAGE COUNTER
IS SET
BY ADDRESS
STROBE IS
TO 010
TO 000
0124 IN S
INHIBITED
BY ADDRESS
0124 IN S
40768
Figure 4-87. Subinstruction SUO, Data Transfer Diagram
4-174
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
70446
EM
CH
S
6031
ws
1 4312
G
166031 WG# 000000
l WG 007004 '
1 170446
B
166031 (007
004) (00<
31^
A
007004 RA i
L
Q
Z
004312 R Z i
u
004312
Y
004311
X
000000
Cl
1
SO
166
TIME 1 2 3 4 5 6 7 8 9 10 II 12
STAGE RSC IS TSGN TPZG SETS ST2 SETS
COUNTER NOT USED SETS C(BR) = 00 STAGE
IS SET BY BZMFO C(BR) = OX- COUNTER
TMZ IS
NOT USED
BY BZMFO
TO 010
40769
Figure 4-88. Subinstruction BZMFO with Quantity Greater Than Plus Zero,
Data Transfer Diagram
4-175
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
. *0770
Figure 4-89. Sub instruction BZMFO with Plus Zero, Data Transfer Diagram
4-176
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
70446
EM
CH
S
6031
WSA0446
M70446)
G
166031 WG« 000000 ,
LWG 164202 1 170446 RAD'
(170
446)
B
166031 (l64
202) > RB
' WB
170446 RB '
A
164202 RA<
L
Q
U66
03l)
Z
004312
WZA006032
(006032) 070
446 )
u
004312
Rui 006032
Y
004311 WYI2 '
006031
X
000000 WYI 2 #000000
Cl
1 1
so
166
WSQY070
TIME
2
3
4
5 6
7
8
9
10
II
12
STAGE
COUNTER
IS SET
TO 000
RSCIS
NOT USED
BY BZMFO
TSGN
SETS
CIBRMX-
TMZ IS
NOT
USED BY
BZMFO
TPZG
SETS
C(BR) = IO
Cl SETS
CARRY
FLIP-FLOP
NISO
CAUSES
RB AND
WSQ AT
TIME 12
40771
Figure 4-90. Subinstruction BZMFO with Negative Quantity, Data Transfer Diagram
4-177
ND-1021042
MANUAL LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
FM
1 00006
EM
CH
S
2035
WS,
1244
6
162035 WG*000000 ,
WG 003210
000006
B
162035 (OCX
2K))
RB i
A
003210 RA ‘
• (oo|
?44)
L
0
Z
001244 RZ
U
001244
Y
001243
X
000000
Cl
1
SO
162 162 WSQ'
r 102
TIME
2
3
4
5
6
7
8
STAGE
RSC IS
TSGN
TPZG
EXTPLS
COUNTER
NOT
ANO
SETS
SETS BIT
IS SET
USED BY
TMZ SET
C(BR)-00
EXT OF SO
TO 000
BZMFO
C(BR) = OX
ST2 SETS
STAGE
COUNTER
TO 010
Figure 4-91. Subinstruction BZMFO with Implied Address Code EXTEND,
Data Transfer Diagram
4-178
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
T
EM
00002 |
,00002
CH
1
1
S
0521
WS * 6534
1
1
G
170521 WG^ 000000
1
000002 f RG*
>000002
( 000002 )
B
170521 J WB A 012345 '
► R8 WB *00000 2
R8
’ WB A 000002
(OOOOOg) (012345)
(006
534)
(ooooop)
fl
012345 RScl HA • (012345)
WA? 000000
L
001700 RSC 1 WL'
7012345
0
RSC |
(000
002) (poo
002)
z
006354 RSC i RZ •
u
006534
RU (
000002
Y
006533 WY '
000002
X
000000 WY *000000
Cl
1 *0
SO
170
TIME
2
3
4
5
6
7
8
9 10
II
12
STAGE
RSC IS
TSGN
FIXED
TSGN 2
TSGN SETS
COUNTER
INHIBITEO
SETS
MEMORY
SETS
C(BR)-OX
IS SET
8YAD0RESS
C(BR)"0X
STROBE IS
C(BR)*00
STI SETS
TO 000
0521 INS
INHIBITEO
STAGE COUNTER
BY AOORESS
TO 001
0521 IN S
NEACON
INHIBITS END
AROUND
CARRY
40773
Figure 4-92. Subinstruction MPO with Two Positive Numbers, Data Transfer Diagram
4-179
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
177775
,77775
CH
S
0521
ws,
6534
G
170521 WG^OOOOOO
' 177775 RG.
1177775
! O
B
170521 ] WB A 012345 '
RB » 177775
RB 1
WB
1 177776
(goooog) (012345) (012
345) (006
534)
U77777)
A
012345 RSC j RaI
▼177777
L
001700 RSC| Wl'
012345
LI6
112345
Q
RSC 1
775) (l77
776)
Z
006534 RSC 1 RZ<
U
006534
RU1
'177776
Y
006533 WY'
177775
X
000000 WY« 000000
Cl
1 1
SO
170
TIME
1
2
3
4
5
6
7
8
9
10
II 12
STAGE
RSC IS
TSGN
TSGN2
TSGN SETS
RBI
COUNTER
INHIBITED
SETS
SETS
C(8R)= IX -
AND
IS SET
BY
C(BR) = OX
CIBRhOI
NEACON
RIC
TO 000
ADDRESS
INHIBITS
PLACE
0521 IN S
END AROUND
177777
CARRY
ON WRITE
STARTING
WITH TIME 10-
LINES
STI SETS STAGE
COUNTER TO 001
Figure 4-93. Subinstruction MPO with Positive Number in A and 40774
Negative Number in E, Data Transfer Diagram
4-180
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
t
EM
00002 1
I
CH
1
1
S
0521
1 ws(
1
6534
1
1
1
6
170521 WG | OOOOOO ’
1
000002 + RGf
| (000002)
B
1
170521 1 WB A 165432
|RC 012345 WBT000002
RC<
'177775
1 WB 177776
(OOOOOO) U65432)
(006
534)
(j77777)
A
165432 RSc| RA# (oi2
345)
WAf 177777
L
001700 RSC +
1
1 012345
LI6
112345
0
RSC +
I
'€
p) p
776)
z
1
006534 RSCi RZ'
u
006534
RU'
U77776
Y
006533 WY
177775
X
OOOOOO WY #000000
Cl
1 1
SO
170
TIME
1 2
3
4
5 6
7
8
9
10
II
STAGE
RSC IS
TSGN
FIXED
TSGN2
Cl SETS
TSGN
RBI AND
COUNTER
INHIBITED
SETS
MEMORY
SETS
CARRY
SETS
RIC
IS SET
BY
C(BR)= IX
STROBE IS
C(BR)=IO
FLIP-
C(BR) = IX-
PLACE
TO 000
ADDRESS
INHIBITED
FLOP
STI SETS
177777
0521 IN S
BY
STAGE
ON
ADDRESS
COUNTER
WRITE
0521 IN S
TO 001 -
LINES
NEACON
INHIBITS
END AROUND
CARRY
12
40775
Figure 4-94. Subinstruction MPO with Negative Number in A and
Positive Number in E, Data Transfer Diagram
- Nk
4-181
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
•
1
EM
•177775
1
CH
1
1
S
0521
1
I ws
,6534
1
1
1
G
170521 WG ^OOOOOO
177775 | •
1 .
| (177775)
1
8
170521 1 W8 A 165432 i
1_ I
|RC 012345 WBf 177775
RC
000002
iWB 000002
(60OOOO) (165432)
(6o6
534)
(OOOOOO)
A
RSC • RaI (ot2
1 ^1
S45)
WA ? OOOOOO
L
001700 RSC* WL'
1
012345
Q
1
RSC •
1
(000
002) (000
002)
Z
1
006534 RSC* RZJ
u
006534
RU 1
000002
Y
006533 WY’
000002
X
000000 WY *000000
Cl
1 *0
SO
170
TIME
STAGE
COUNTER
IS SET
TO 000
RSC IS TSGN
INHIBITED SETS
BY ADDRESS C(BR) = IX
0521 IN S
FIXED
MEMORY
STROBE IS
INHIBITED
BY ADDRESS
0521 IN S
TSGN2
SETS
C( BR) =
10
TSGN SETS
C(BR) = OX
STI SETS
STAGE
COUNTER TO
001 NEACON
INHIBITS END
AROUND
CARRY
40776
Figure 4-95. Subinstruction MPO with Two Negative Numbers, Data Transfer Diagram
4-: -182
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
TIME 1
2
3
4
5
6
7
8
9
10
STAGE
Cl
STI AND
COUNTER
SETS
ST2 SET
IS SET
CARRY
STAGE
TO OOI
FLIP-
COUNTER
FLOP
TO Oil
40777
Figure 4-96. Sub instruction MP1, Data Transfer Diagram
4-183
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
1 1012 1
EM
T
t
CH
i
1
l
1
1
S
6534 1
1
ws,
,0121
1
1
(oic
!
G
034512 L2G0 #047122 WG ^000000
0 1 01 2 1 RAO'
i
•
i €
I2n
B
000002 RB'
1 !
1 | WBY0I0I2I RB
|
^00000)
A
WALSi
000000
WALS
1
000000 #RSC
1
L
WALS
G2LS1
023451
WALS
G2LS
1
024412 • RSC
1
0
(000
002) (000
002)
1
• RSC
1
z
006534
(ooc
Oo£) #RSC RZi
' WZ,
,006535
(006
534) (006535) (OK
u
RU<
000002
RU<
'000002
RU i
006535
Y
000002 WY'
000002 WYI2'
006534
X
000000 A2X# 000000 WYI2# 000000
Cl
0 #0 #1
SO
170 WSQ'
010
TIME 1
2
3 4 5
6 7
8
9
10
STAGE
NISO
RSC AND Cl SETS
TLI5
RA IS
RL IS
COUNTER
CAUSES
ERASABLE CARRY
SETS
NOT USED
NOT USED
IS SET
RB AND
MEMORY FLIP-
C(BR)sOX -
BY MP3
BY MP3 -
TO Oil
WSO AT
STROBE FLOP
NEACOF
ERASABLE
TIME 12
ARE
PERMITS
MEMORY
INHIBITED BY
END
STROBE
AODRESS
AROUND
IS INHIBITED
6534 IN S
CARRY
BY ADDRESS
6534 IN S
40778
Figure 4-97. Subinstruction MP3, Data Transfer Diagram
4-184
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
1 00006
EM
•
1
t
CH
1
1
1
1
S
6534
ws,
6535
1
1
1
1
G
034512 L2GD*047I22 Wg|oOOOOO
000006
1
•
1
1
B
000002 RB <
1
| WB
|
,006535 RB'
(OOOOOO) (006
A
WALS i
000000
WALS i
1
OOOOOO • RSC
r
L
WALS
G2LS'
023451
WALS
G2LS'
1
,024712 • RSC
1
Q
(6oo
002) (000
M2)
1
• RSC
1
Z
006534
(MO
302) *RSC RZ* WZ|
t 006535 RZ '
(RAD)
(006
534) (006535) (006
U
000002 '
1 RU
RU'
000002
RU<
•006535
r
Y
000002 WY •
000002 WYI2 '
006534
X
000000 A2X *000000 A2X* 000000
Cl
•
o
•
o
so
170
170
WS2TI00
TIME
|
2
3 4
5
6 7
8
9
10 II
12
STAGE
NISO
RSC AND
Cl SETS
TLI5 SETS
EXTPLS
RA IS
RL IS
COUNTER
CAUSES
ERASABLE
CARRY
C( 8R ) = OX -
SETS BIT
NOT USED
NOT USED
IS SET
R8 AND
MEMORY
FLIP-
NEACOF
EXT OF SQ-
BY MP3
BY MP3 -
TO 01
WSO AT
STROBE
FLOP
PERMITS
ST2 (RAD)
ERASABLE
TIME 12
ARE
END
SETS
MEMORY
INHIBITED
AROUND
STAGE
STROBE IS
BY ADDRESS
CARRY
COUNTER
INHIBITED
6534 IN S
TO 010
BY ADDRESS
6534 IN S
40779
Figure 4-98. Subinstruction MP3 with Implied Address Code EXTEND,
Data Transfer Diagram
4-185
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
I
Figure 4-99. Sub instruction GOJ1, Data Transfer Diagram
4-186
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00102
, 00103
CH
. s
0234 AWS0024
WS
k 0234
(000024)
(OIO
234)
G
010234 '
000102
1 RG WG
,000103
000103
B
010234
RB 1
A
L
(000
io2) (OOC
K)3)
0
z
006371
u
006371
RU(
000103
Y
006370 WY’
000102
X
000000 PONE X #000001
Cl
1
SQ
O'O
RSCT
RSC IS
TSGN.TMZ,
WOVR DOES
PLACES
NOT
AND TPZG
NOT CAUSE
COUNTER
USED
ARE NOT
AN INTERRUPT
ADDRESS
BY
USED BY
SINCE NEITHER
ON WRITE
PINC
PINC
OVERFLOW NOR
LINES
UNDERFLOW
OCCURRED -
WSC IS NOT
USED BY PINC
40781
Figure 4-100. Subinstruction PINC, Data Transfer Diagram
4-187
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00046
00045
CH
S
0106 AWS0042
WS
>0106
(6o0042)
(OIO
106)
G
010106 WG • 000000 '
000046
>RG WG
>000045
000045
B
010106
RB '
A
L
(ooc
>46^) (OOC
)45)
0
z
005720
u
005720
RU1
^000045
Y
005717 WY '
000046
X
000000 MONEX# 177776
Cl
1
SO
OIO
TIME
1
2 3
4
5
6 7 8
9
10
II
12
RSCT
RSC IS
TSGN,
WOVRDOES
PLACES
NOT USEO
TMZ.AND
NOT CAUSE
COUNTER
BY MINC
TPZG ARE
AN INTERRUPT
AOORESS
NOT USEO
SINCE NEITHER
ON WRITE
BY MINC
OVERFLOW NOR
LINES
UNDERFLOW OCCURRED -
WSC IS NOT USED BY
MINC
4-188
Figure 4-101. Sub instruction MINC, Data Transfer Diagram
4078?
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00444 (
00443
CH
S
0111 AWS 0050
WS,
OKI
(000050)
( ISC
"0
G
1501 1 1 WG *000000
000444
• RG WG,
000443
^000443
B
1 5011 1
A
L
(ooo
444) (OOO
443)
Q
Z
007210
U
007210
Y
007207 WY '
000444 RU<
000443
X
000000 WY* 000000 MONEX* 177776
Cl
1 0
SQ
050
TIME
1
2 3
4
5
6
7 8
9
10
II
12
STAGE
RSCT
RSC IS
TSGN.
POUT
WSC IS
COUNTER
PLACES
NOT USED
TMZ.AND
CAUSES
NOT USED
IS SET
COUNTER
BY DINC
TPZG
POSITIVE
BY DINC -
TO 000
ADDRESS
SET
RATE
WOVR DOES
ON WRITE
C(BR) = 00
OUTPUT
NOT CAUSE
LINES
PULSES
AN INTERRUPT
SINCE NEITHER
OVERFLOW NOR
UNDERFLOW
OCCURRED
40783
Figure 4-102. Sub instruction DINC with Positive Quantity, Data Transfer Diagram
4-189
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
STAGE RSCT
COUNTER PLACES
IS SET COUNTER
TO 000 ADDRESS
ON WRITE
LINES
RSC IS
NOT USED
BY DINC
TSGN.
TM Z .
AND
TPZG
SET
C(BR)*OI
ZOUT
REMOVES
RATE
OUTPUT
PULSES
WSC
IS NOT USED
BY DINC-
WOVR DOES
NOT CAUSE
AN INTERRUPT
SINCE NEITHER
OVERFLOW
NOR UNDERFLOW
OCCURRED
Figure 4-103. Subinstruction DINC with Plus Zero, Data Transfer Diagram
4-190
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
TIME
STAGE
COUNTER
IS SET
TO 000
RSCT
PLACES
COUNTER
ADDRESS
ON WRITE
LINES
RSC IS
NOT USED
BY OINC
TSGN,
TMZ. AND
TPZG
SET
CIBRI--IO
MOUT
CAUSES
NEGATIVE
RATE
OUTPUT
PULSES
WSC IS
NOT USED
BY DINC -
WOVR DOES
NOT CAUSE
AN INTERRUPT
SINCE NEITHER
OVERFLOW NOR
UNDERFLOW
OCCURRED
40785
Figure 4-104. Subinstruction DINC with Negative Quantity, Data Transfer Diagram
4-191
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
i77777 ,
77777
CH
S
0111 WS A 0050
* WS 1
r
(000050)
IIM
G
1 5011 1 WG«000000
177777
RG WG,
,177777
1 177777
0
1501 II
RB'
A
L
( 177
■77) (jrT
0
r
z
007210
u
007210
RU
1 177777
Y
007207 WY '
177777
X
000000 WY»000000
Cl
1 0
SO
050
TIME
1
2
3
4
5
6
7
STAGE
RSCT
RSC IS
TSGN
ZOUT
WSC IS NOT
COUNTER
PLACES
NOT
TMZ
REMOVES
USED BY
IS SET
COUNTER
USED
ANO
RATE
DINC -
TO 000
ADDRESS
BY
TPZG
OUTPUT
WOVR DOES
ON WRITE
DINC
SET
PULSES
NOT CAUSE
LINES
CLBRMI
AN INTERRUPT
SINCE NEITHER
OVERFLOW NOR
UNDERFLOW OCCURRED
10 II 12
Figure 4-105. Subinstruction DINC with Minus
Zero, Data Transfer Diagram
40786
4-192
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
00103 i
00104
CH
S
0133 AWS 0032
WS,
,0133
(000032)
(010
33)
G
010133 WG #000000
000103
• RG WG
i 000104
'000104
B
010133
RB'
'OIOI33
A
(ooo
104)
L
(ooo
KD3)
Q
Z
001222
u
001222
RUS '
000104
Y
OOI22I WY1
000103
X
000000 WY* 000000
Cl
l
SO
010
•
TIME
1
2
3
4
5
6
7 8
9
10
II
12
STAGE
RSCT
RSC IS
TSGN.
Cl
WOVR DOES
COUNTER
PLACES
NOT
TMZ,
SETS
NOT CAUSE
IS SET
COUNTER
USED
AND TPZG
CARRY
AN INTERRUPT
TO OOO
ADDRESS
BY PCDU
ARE NOT
FLIP-
SINCE NEITHER
ON WRITE
USED BY
FLOP
OVERFLOW NOR
LINES
PCOU
UNDERFLOW
OCCURRED -
WSC IS NOT
USED BY PCDU
40787
Figure 4-106. Subinstruction PCDU, Data Transfer Diagram
4-193
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
1 00336
00335
CM
S
1164 AWS 0035
WS
1 1164
(000035)
( Oil
164)
G
01 1 164 WG • 000000
000336
1 RG WG
1 000335
000335
B
011 164
RB i
A
L
(ooo
336) (OOC
Q
Z
001334
U
001334
RUSi
000335
Y
001333 WY
000336
X
MONEX
000000 WY #000000 #177776
Cl
1 1
SO
Oil
TIME
1
2
3
4 5
6
7 B
STAGE
COUNTER
IS SET
TO 000
RSCT
PLACES
COUNTER
ADDRESS
ON WRITE
LINES
RSC IS
NOT USED
BY MCDU
TSGN,
TMZ, AND
TPZG ARE
NOT USED
BY MCDU
Cl SETS
CARRY
FLIP-
FLOP
WOVR DOES
NOT CAUSE
AN INTERRUPT
SINCE NEITHER
OVERFLOW
NOR UNDERFLOW
OCCURRED -
WSC IS
NOT USED
BY MCDU
40788
Figure 4-107. Subinstruction MCDU, Data Transfer Diagram
4-194
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
•05530
1 13260
CH
S
2123 AWS 0045
WS
i 2123
(000045)
U52
I23j
G
152123 WG*000000
005530
• RG 005530 WG
>013260
013260
8
152123
RB •
A
L
(005
530) (013
260)
0
z
001664
u
001664
RUS(
013260
Y
001663 WYD1
013260
X
oooooo wyo#oooooo
Cl
1 0
SO
052
TIME I 2
STAGE RSCT RSCIS
COUNTER PLACES NOT USED
IS SET COUNTER BY SHINC
TO 000 ADDRESS
ON WRITE
LINES
TSGNIS
NOT USED
BY SHINC
WOVR DOES
NOT CAUSE AN
INTERRUPT SINCE
NEITHER OVERFLOW
NOR UNDERFLOW
OCCURRED -WSC IS
NOT USED BY
SHINC
40789
Figure 4-108. Subinstruction SHINC, Data Transfer Diagram
4-195
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
33410
67021
CH
S
3100 AWS 0045
WS
,3100
(000045)
IOO)
G
153100 WG*000000
033410
1 RG WG
167021
167021
B
153100
RB'
A
L
(033
4lo) (\G7
02l)
0
Z
001701
u
001701
RUS '
*067021
Y
001700 WYO'
067020
X
000000 WYO *000000
Cl
1 |
so
053
TIME
1 2
3
4
S 6
7 6
9
10
II
12
STAGE
RSCT RSC IS NOT
TSGN IS
WOVR
COUNTER
PLACES USED BY
NOT USED
CAUSES AN
IS SET
COUNTER SHANC
BY SHANC -
INTERRUPT
TO 000
ADDRESS
Cl SETS THE
SINCE OVERFLOW
ON WRITE
CARRY FLIP-
OCCURRED
LINES
FLOP
40790
Figure 4-109. Subinstruction SHANC, Data Transfer Diagram
4-196
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
S
3024 WS
,1031
G
153024 WG ^ 000000
1
1
B
153024 (OOOOOQ)
1
A
- n
RSC |
L
1
RSC +
Q
RSC 4
Z
1
001444 RSC* WZ,
001031
(oo^
dT?)
U
001444
Y
001443
X
000000
Cl
-
SQ
053
TIME
2
3
4
5
6
7 0
9
10
II
12
STAGE
RSC IS
COMPUTER
COUNTER
INHIBITED
TEST SET
IS SET
BY ADDRESS
PLACES
TO 000
3024 IN S
ADDRESS ON
WRITE LINES -
ST 2 SETS
STAGE
COUNTER
TO 010
40791
Figure 4-110. Sub instruction TCSAJ3, Data Transfer Diagram
4-197
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
BB
030006 RSO
WSC,
S
0300 *WS 000006
WS *0343
(000006) (030
006) (boo-
003) (000343)
G
020300 WG
030006
B
020300
A
L
Q
Z
001664
u
001664
Y
001663 WY
030006
X
000000 WY • 000000
Cl
1 0
SQ
020
TIME
1
2
3
4
5
6
7
8
9
10
II
12
STAGE
R6
STI
COMPUTER
COMPUTER
COUNTER
PLACES
SETS
TEST SET
TEST SET
IS SET
000006
STAGE
PLACES
PLACES
TO 000
ON
COUNTER
BANK
ADDRESS
WRITE
TO 001
ADDRESS
ON WRITE
LINES
ON WRITE
LINES
LINES
<079?
Figure 4-111. Sub instruction FETCHO, Data Transfer Diagram
4-198
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
A
RSC '
\
L
RSC <
0
RSC <
z
001664 RSC 1
u
030006
Y
030006
X
000000
Cl
0
SO
020
TIME
1
2 3
4
5
6
7
8 9
10 II 12
STAGE
RSC IS
FIXED
C(G ) IS
U2BBK
RBBK
COUNTER
INHIBITED BY
MEMORY
PLACED
MAY BE
PLACES
IS SET
ADDRESS
STROBE IS
ON
INHIBITED
CIBBI ON
TO 001
0343 IN S
INHIBITED
WRITE
BY COMPUTER
WRITE LINES
BY
LINESAND
TEST SET
FOR DISPLAY
ADDRESS
DISPLAYED
BY COMPUTER
0343 IN S
BY
TEST SET
COMPUTER
TEST SET
40793
Figure 4-112. Subinstruction FETCH1, Data Transfer Diagram
4-199
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FM
EM
CH
030006 RSC
i wsc
1
S
0400 * WS000006
WS A 0246
( ^00006 ) (030
006) (OOC
003) (000246)
G
020400 WG
’030006
8
020400
A
L
0
Z
001600
u
001600
Y
001577 WY '
r030006
X
000000 WY #000000
Cl
1 0
TIME
1
2 3
4 5
6
7
8
STAGE
COUNTER
IS
SET
TO 000
R6 PLACES
000006
ON WRITE
LINES
STI SETS
STAGE
COUNTER
TO 001
COMPUTER
TEST SET
PLACES BANK
ADDRESS
ON WRITE
LINES
COMPUTER
TEST
SET PLACES
ADDRESS
ON WRITE
LINES
40794
Figure 4-113. Subinstruction STOREO, Data Transfer Diagram
4-200
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
EM
* 73221
, 34000
CH
U2BBK • 030006
S
024 G
WSI
^ 0400
G
030006 WG ^000000
173221 (020
4°0) WG A 034000
'034000
1
1
(034000)
B
020400 (OOOOOp) RB
1
i
A
RSC | WSC*
L
RScj WSC .
0
RScj WSCi
z
001600 RScl WSC i
U
030006
Y
030006
X
000000
Cl
0
TIME
2
3
4 5
6
7
8
9
10
STAGE
RSC IS
WSC IS
RG IS
U2BBK
COMPUTER
RBBK
COUNTER
NOT
INHIBITED BY
NOT
MAY BE
TEST SET
PLACES
IS SET
USED
ADDRESS
USEO
INHIBITED
PLACES
CIBBI
TO 001
BY
0246 IN S
BY
BY
DATA ON
ON WRITE
STORE 1
STORE
COMPUTER
WRITE
LINES FOR
TEST SET
LINES
DISPLAY BY
COMPUTER
TEST SET
40795
Figure 4-114. Sub instruction STORE 1, Data Transfer Diagram
4-201
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
u
001046
Y
001045
X
000000
Cl
'
SO
051
TIME
1
2
3
4
5
STAGE
COMPUTER
RSC IS
C(CH)
COUNTER
TEST SET
NOT USED
PLACED
IS SET
PLACES
INOTRD
ON WRITE
TO 000
ADORESS
LINES IS
ON WRITE
SENT TO
LINES
COMPUTER
TEST SET
40796
Figure 4-115. Subinstruction INOTRD, Data Transfer Diagram
4-202
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
u
001077
Y
001076
X
'00000
Cl
'
SO
053
TIME
1
2
3
4
5
6
7 e
9
10
II
12
STAGE
COMPUTER
RSC IS
C(CH)
COMPUTER
COUNTER
TEST SET
NOT
PLACED
TEST SET
IS SET
PLACES
USED BY
ON WRITE
PLACES OATA
TO 000
ADDRESS
INOTLD
LINES IS
ON WRITE
ON WRITE
SENT TO
LINES
LINES
COMPUTER
TEST SET
Figure 4-116. Sub instruction INOTLD, Data Transfer Diagram
40797
4-203
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
4-5.3 TIMER. The timer generates all timing functions required for operation of the
LGC. In addition, the timer is the primary source of all timing and sync signals for
all the LEM systems.
4-5. 3.1 Timer Functional Description. Timer operation contains the functional areas
indicated in figure 4-117. These functional areas include the LGC oscillator, clock
divider logic, scaler, time pulse generator, and the sync and timing logic. The LGC
oscillator is a crystal controlled, modified Pierce oscillator design that generates a
source frequency of 2.048 me for the clock divider logic. Temperature compensated
components in the LGC oscillator circuit maintain a high degree of stability and assure
an extremely accurate output frequency to the clock divider logic.
The clock divider logic is further subdivided into the main clock divider, ring
counter, and strobe pulse generator. The 2.048 me input from the LGC oscillator is
applied to the main clock divider. The main clock divider divides the input frequency
by two and generates the following outputs: clear, write, and read control pulses
(CT, WT, RT) which are applied to the central processor to produce the signals
necessary to clear, write into, and read out the flip-flop registers; 1.024 me gating
pulses (PHS2, PHS3, PHS4, OVFSTB, TT) which are used throughout the LGC; the mas¬
ter clock signal (CLK), a 1.024 me output used to synchronize the other LEM systems;
and signal Q2A which is applied to the oscillator alarm circuit in the power supply to
indicate LGC oscillator activity. In addition, the main clock divider supplies signals
(RlNG A and RING B) to drive the ring counter, and signals (EVNSET and ODDSET) to
the time pulse generator. These latter outputs occur at a 512 kc rate, a result
of further division of the 1.024 me gating rate within the main clock divider.
The ring counter generates outputs (P01 through P05) at a 102.4 kc rate. The
outputs are 5 microsecond pulses used for gating and for deriving other timing functions
in the LGC. Ring counter outputs are also used to derive the strobe pulses (SB0, SB1,
SB2, SB 4) from the strobe pulse generator. These outputs also occur at a 102.4 kc
rate and are 3 microseconds in width with the exception of SB4, which is a 2 micro¬
second pulse.
The scaler consists of 33 identical divider stages. The stages are cascaded so
that the frequency division is successive. The first stage, driven by signal P01
from the ring counter, generates outputs at a rate of one-half the input or 51.2 kc.
This output and the remaining outputs through stage 17 (0.78125 pps) are used for
timing and gating. The outputs appear as signal outputs from flip-flop circuits (FS01,
etc.), and 10 microsecond pulse outputs (F01A, etc.) at the same frequency as the
associated stage. Stages 6 through 19 and 20 through 33 form a 28 bit real time word
(CHAT01 through CHAT14, CHBT01 through CHBT14) which indicates time intervals up
to 23.3 hours.
_ time pulse generator, consisting of 12 flip-flop circuits, generates timing
pulses T01 through T12. This sequence of timing pulses defines one MCT within the
LGC, or a period of 11.97 microseconds, in which word flow takes place. The time
pulse generator is driven by inputs (EVNSET and ODDSET) from the main clock divider.
4-204
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND 1021042
MANUAL
CLOCK DIVIDER LOGIC
OSCILLATOR
(FROM PRIORITY
CONTROL)
MAIN
OIVIOER
LOGIC
L
CLEAR. WRITE. ANO
WT > READ CONTROL
PULSES
PHS2
phsT
PHS4 >
GATING PULSES
OVFSTB
TT
)
}
I 024 MC MASTER
CLK > CLOCK TO SPACE¬
CRAFT SYSTEMS
TO OSCILLATOR
ALARM CIRCUIT
512 KC GATING
PULSES
STROBE
PULSE
GENERATOR
— ► SBo'j
— ► SAI 1 102 4KC
> GATING
— ► SB2 PULSES
— *• SB4J
TE
RING
COUNTER
— ► POl'
_ 102.4 KC
— ♦ P03 V GATING
pQ4 PULSES
— ► P05
1
j
INPUT-OUTPUT
GATING ANO
STROBE SIGNALS
PULSE OUTPUTS
TO PROGRAM
TIME COUNTERS
LGC ANOOSKY
POWER SUPPLY
SYNC SIGNALS
EXTERNAL SYSTEMS
SYNC SIGNALS
ODOSET
TIME
PULSE
GENERATOR
TO I
TIMING PULSES
(ONE MEMORY
CYCLE Tl ME -
11.97 USEC)
TI2 SET
FSOI-FS33
>}
SIGNAL
OUTPUTS
SCALER
» FOIA-F33A
» FOIB-F33B
— ► FOIC, F07C
PULSE
OUTPUTS
FOID, F05D.F09D
CHATOI-CHAT 14
CHBT0I-CHBTI4
REAL
TIME
WORD
16082
Timer, Functional Diagram
4-205/4-206
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Signal ODDSET can be inhibited by signal STOP from priority control. Signal STOP,
an input from the CTS during preinstallation system and subsystem tests, inhibits the
time pulses from being generated thus preventing word flow in the LGC. This feature
allows individual memory cycle times to be observed during tests.
The sync and timing logic consists of a gating complex which generates various
outputs for use within the LGC, and synchronization signals for systems external to
the LGC. The inputs to, and outputs from, this section are extensive, and are grouped
by function in figure 4-117.
The ring counter, strobe pulse generator, and the scaler supply inputs to the sync
and timing logic. These inputs are used to derive gating and strobe signals for the
input and output channels, pulse outputs for the program time counters in memory, and
synchronization signals for the LGC and DSKY power supplies and for systems external
to the LGC.
During standby operation, the LGC oscillator, clock divider logic, and the scaler
are operative and generate the signals associated with these functional areas. However,
the significant outputs during this mode of operation are the real time word from the
scaler find the synchronization signals to the other LEM systems. The real time
word continues to be accumulated during standby, and the external systems synchro¬
nization signals continue to be generated.
4-5. 3. 2 LGC Oscillator Detailed Description. The LGC oscillator (figure 4-118)
generates a master clock frequency of 2.048 me. The basic LGC oscillator circuit,
consisting of crystal Yl, and transistor Q1 and associated components, is a modified
Pierce oscillator design. Variable inductor LI, in series with the crystal, compensates
for frequency drift due to component aging. The crystal output is amplified by tran¬
sistor Ql, which operates as a class A amplifier that drives buffer stage Q2. The
sinusoidal output of stage Q2 is applied to pulse shaper Q3 and, through capacitor C7,
to a dc feedback network. The output of the feedback network controls the peak-to-peak
output level of stage Ql. The resultant 2.048 me square wave output of stage Q3 is
amplified by output stage Q4, and is applied to the clock divider logic.
The collector supply voltage for stages Ql and Q2 is obtained from the +14 volt
output (B PLUS) of the power supply. This voltage is applied through resistor R5 and
is regulated by zener diode CR1 (rated at 9 volts). The +4 volt power supply output is
furnished directly as the collector supply for stages Q3 and Q4.
Two resistor networks (R4, R6, RIO, R9, R12 and R2, R3, R7, R8, Rll), in conjunc¬
tion with thermistors RT1, RT2, and RT3 and varicap CR2, comprise the temperature
compensation network which improves the stability of the LGC oscillator. The regulated
output voltage of diode CR1 is applied across the two resistor networks, the outputs of
which are applied across varicap CR2. The varicap is a reverse-biased diode that
introduces capacitance into the circuit. Any changes in temperature cause a corre¬
sponding change in the reverse bias across the varicap thus varying the effective capa¬
citance in series with crystal Yl, which is also affected by the change in temperature.
4-207/4-208
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
[b7
NOTE: NOMINAL RESISTOR VALUES ARE
ESTABLISHED AT ELECTRICAL TEST
J
Figure 4-118. LGC Oscillator
Schematic Diagram
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
4-5. 3. 3 Clock Divider Logic Detailed Description. The clock divider logic consists
of the main clock divider, ring counter, and strobe pulse generator. The main clock
divider (figure 4-119, sheet 1) generates outputs at the basic clock rate of the system,
1.024 me. In addition, 512 kc outputs drive the ring counter and the time pulse gen¬
erator. The 2.048 me CLOCK input from the LGC oscillator is applied to the first
main clock divider circuit consisting of gates 37101 through 37106. Gates 37101
through 37104 are interconnected in a manner similar to the basic flip-flop
circuit of the LGC. Gates 37105 and 37106 function as a flip-flop; however, gates
37101 through 37104 do not. The waveforms in figure 4-119 indicate that an output
occurs from only one of the four gates at each positive and negative transition of the
clock input. The other three gates remain in ZERO state. Unlike a flip-flop, in
which one side is ZERO while the other side is a ONE and vice-versa, this circuit
resembles a ring counter. The outputs of these four gates (37101 through 37104) are
used to derive the clear control signal (CT), read control signal (RT), and the three
1.024 me gating pulses (PHS2, PHS3, and PHS4) which are 0.25 microseconds wide.
The outputs from gates 37102 and 37103 drive FF37105-37106, which is alter¬
nately set and reset at 1.024 me rate. The write control signal (WT) and the 1.024 me
master clock (CLK) signal to the LEM systems are derived from this flip-flop output.
Any failure of the LGC oscillator would be most directly indicated by the output of
the first main clock divider circuit. Thus, signal Q2A is applied to the oscillator
alarm circuit in the power supply to indicate LGC oscillator activity. The output
is from an extended NOR gate which has its collector load in the alarm circuit. Figure
4-119 illustrates the timing relationship between the clear and write control signals.
The 0.25 microsecond clear pulse is coincident with the first 1/4 microsecond of the
0.5 microsecond write control signal. The read control signal is 0.75 microsecond wide.
All three of these control signal outputs are applied to the central processor for clear¬
ing, writing into, and reading out of the flip-flop registers. The clear pulse (CT) is
used also to derive the overflow strobe signal (OVFSTB), a 1.024 me gating signal.
This output is shown wider than the clear pulse since some propagation delay undoubt¬
edly exists to stretch this pulse slightly beyond 0.25 microsecond before FF37148-
37149 resets.
The inverted output of gate 37101 drives the second main clock divider circuit
which consists of gates 37111 through 37114 and FF37117-37118. Outputs from this
circuit drive the ring counter (RING A, RINGB) and the time pulse generator (ODDSET,
EVNSET). The outputs occur at a 512 kc rate, and are 90 degrees out of phase with
each other (see figure 4-119). This main clock divider circuit is identical in operation
to the first main clock divider circuit. Each of the gates 37111 through 37114 generates
in succession an output on each transition of the output of gate 37107. Output pulses
from gates 37112 and 37113 alternately set and reset FF37117-37118. No output
signals are derived from this flip-flop. The outputs to drive the ring counter and the
time pulse generator are obtained from gates 37111 and 37114. Signals RING A and
ODDSET from 37111 occur coincidentally, and RING B and EVNSET from 37114 occur
coincidentally. Signal ODDSET, applied to the time pulse generator, can be inhibited
by input STOP from priority control, which prevents any outputs from the time pulse
generator and subsequently inhibits word flow in the LGC. This feature can be
4-211/4-212
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
4-213/4-214
ND-1021042
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM MANUAL
4-215/4-216
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
employed during pre-installation system and subystem tests as a result of a monitor
stop (MSTP) input from the CTS.
The ring counter (figure 4-119, sheet 2) consists of five flip-flop circuits with
outputs labeled P01 through P05 (and P01 through P05). The ring counter is driven
by inputs (RING A and RING B) from the main clock divider. Each of these inputs,
described previously, occurs at a 512 kc rate. The ring counter does not accomplish
a division-by-two. Rather, the division by the fives stages results in five symmetrical
outputs, each at a rate of 102.4 kc and 5 microseconds in width. Successive outputs
occur 1 microsecond apart; for example, P02 occurs 1 microsecond after P01 etc.
Strobe pulses SBO, SB1, SB2, and SB4 are generated by signals P02 through P05
(and complements) from the ring counter. These strobes are 3 microsecond pulses
occurring also at a rate of 102.4 kc, (with the exception of SB4 which is 2 microseconds
wide). Strobe signals SBO, SB1, and SB2 are inverted by gates on module A24 (see
figure 4-119).
4-5. 3.4 Scaler Detailed Description. The scaler, figure 4-120, consists of 33 identical
divider stages. The stages are cascaded to provide successive frequency division of
the input to the scaler. Stage 2 runs at half the rate of stage 1, stage 3 at half the rate
of stage 2, etc. Each of these stages is identical in operation to the main clock divider
circuit in the clock divider logic. The input to the scaler, signal P01 from the ring
counter, occurs at a rate of 102.4 kc. It is applied to stage 1 located on module A2
(the remaining stages of the scaler are located on module Al). Stage 1 divides this
input by two and generates outputs at a rate of 51.2 kc. There are five outputs avail¬
able from stage 1): four pulse outputs (F01A through F01D) from the input gates (37221
through 37224), and one flip-flop output (FF37225-37226).
The pulse outputs of stage 1 are 5 microseconds wide. The period of the flip-
flop output is approximately 20 microseconds; since the output waveform is symmetri¬
cal, the transitions are 10 microseconds apart. Ihe output of the stage 1 flip-flop is
the input to stage 2 of the scaler. Stage 2 divides the input by two and generates outputs
at a rate of 25.6 kc. Three outputs are available from stage 2: two pulse outputs
(F02A, F02B), and the flip-flop output (FS02). The pulse outputs of this stage and all
subsequent stages of the scaler, regardless of frequency, are 10 microseconds wide.
This width is established by the 10 microsecond input from stage 1 to stage 2 and the
fact that a pulse output, not the flip-flop output, feeds stage 3 (F02A). The same is
true of the output from stage 3 to stage 4 (F03A) and of the succeeding scaler stages.
Figure 4-121 illustrates the output waveforms from stages 1 and 2 of the scaler.
The outputs from stage 2 are typical of the outputs from the remaining stages of the
scaler, with the exception of stages 5, 7, and 9. Stages 5 and 9 have one additional
pulse output (F05D, F09D) and stage 7 two additional pulse outputs (F07C, F07D).
These outputs are generated by gates on module A24 as indicated in figure 4-120.
Most of the pulse outputs designated A and B, which are positive going, are in¬
verted by gates contained in other modules. These gates, and the modules in which
they are located, are also illustrated in figure 4-120.
4-217/4-218
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
FSOI
A2
_ J
& 108 ^ 3809^0—
FS06
OIIT^O 1 o'3
- ► FSI4
261
] 382700
-O - ► CHAT04
» O263 - fOOA
— — j 382700-
i - j 382 700 — i
405914 I Of 2
Figure 4-120. Scaler (Sheet 1 of 2)
4-219/4-220
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
-j 49418^0-
FS05
240
- ^4923^0—
-O - ►F05A
A 24
» 32 7-j 463^6^)0 - O-
- O-
• 322 j 4630^0 - O-
FO60
AI9
AI3_
-j 4 124^0 - (>
-j 4526^0-
AI8__
FI8B + 1 33
^4815^0-
A23
_ J
2 OF 2
Figure 4-120. Scaler (Sheet 2 of 2)
4-221/4-222
I
J
SEC
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
r
o
uj
tf)
a.
o
I
4-223
NOTE- THE OUTPUTS OF STAGE 2 (FS02.F02A.F02B)
ARE TYPICAL OF THE OUTPUTS (EXCLUDING
FREQUENCY) FROM THE REMAINING STAGES
OF THE SCALER.
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
The outputs from stages 1 through 17, at rates from 51.2 kpps to 0.78125 pps,
are primarily used to derive timing, synchronization, and gating signals for the LGC
and other systems. Table 4-VIII lists the frequency, period, and polarity of the
outputs of these stages.
The output of stages 6 through 33 provides an indication of real time in the form
of two 14 bit words addressable as two channels that are similar to the channels of the
input-output section of the LGC. Stages 6 through 19 provide the 14 bit word to the low
order channel CHAT01 through CHAT14, while stages 20 through 33 provide the 14 bit
word to the high order channel CHBT01 through CHBT14. The two channels together
indicate time intervals up to 23.3 hours, in 624 microsecond increments. Both words
are formed by the flip-flop outputs of the respective stages, gated by a read channel
signal (RCHAT or RCHBT). Read signal RCHAT, generated under program control as
a function of octal address 0004, causes the low order bits (stages 6 through 19) to
be placed on the write lines in the central processor; read signal RCHBT, generated
under program control as a function of address 0003, causes the high order bits
(stages 20 through 33) to be placed on the write lines.
4-5.3. 5 Time Pulse Generator Detailed Description. The time pulse generator, con¬
sisting of twelve flip-flop circuits, generates timing pulse outputs T01 through T12.
This sequence of pulse outputs defines one MCT within the LGC and occupies an
interval of exactly 11.97 microseconds, or approximately 12 microseconds. Within this
interval, access to memory and word flow take place within the LGC.
Each of the timing pulses is generated by an associated flip-flop circuit shown in
figure 4-122. The odd numbered outputs (Tol, etc.) are gated by signal ODDSET from
the clock divider logic; the even numbered outputs (T02, etc.) are gated by signal
EVNSET. Only one pulse output occurs at one time. Consider an initial condition
in which signal T12 SET is generated. This signal occurs after timing pulses T01
through Til have all been generated. The set output of flip-flops T01 through Til
are ORed through gates 37355, 37356, 37357, and 37358. When all these inputs are
ZERO, output T12 SET is a ONE (coincident with EVNSET) and sets the T12 flip-flop
(FF37302-37303)_. _ The flip-flop reset output is gated by signal EVNSET generating
signals T12 and T12. Signal MT12 is made available to the CTS when this unit monitors
the LGC during tests. When signal ODDSET occurs (0.97 microsecond later), the T01
flip-flop (FF37305-37306) is set by the output of gate 37304. As this flip-flop sets,
the output is fed back to reset the T12 flip-flop. Simultaneously, signal ODDSET gates
the flip-flop reset output generating signals T01 and T01. Signal EVNSET occurs
0.97 microsecond after ODDSET and the T02 flip-flop sets, which in turn resets the
T01 flip-flop.
The remaining timing pulses are generated in this manner except for the T12
output. Since T12 is generated as a function of the T12 SET signal, there is no feedback
from the T12 flip-flop to reset the Til flip-flop. The Til flip-flop is set when output
TlO and ODDSET are coincident, and reset when signal EVNSET is coincident with the
set output (now logic ZERO) of the TlO flip-flop.
4-224
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 4- VIII. Scaler Outputs (Stages 1-17)
Output
Frequency
Period
Pulse Polarity
FS01, FSOl
51.2 kpps
19. 5 /Li sec.
-
F01A, FOIB, FOIC, FOID
Positive
FS02, FS02A
25. 6 kpps
39. 0 /isec.
-
F02A, F02B
Positive
FS03, FS03A
-
F03A, F03B
12. 8 kpps
78. 0 /i sec.
Positive
F03B
Negative
FS04, FS04A
-
F04A, F04B
6.4 kpps
156 usee.
Positive
F04B
Negative
FS05, FS05, FS05A
-
F05A, F05B, F05D
3. 2 kpps
312 /isec.
Positive
F05A, F05B
Negative
FS06, FS06
-
F06A, F06B
1. 6 kpps
624 (1 sec.
Positive
F06B
Negative
FS07 , FS07, FS07A
-
F07A, F07B
800 pps
1. 25 msec.
Positive
F07A, F07B, F07C, F07D
Negative
FS08, FS08
-
F08A, F08B
400 pps
2.5 msec.
Positive
F08B
Negative
(Sheet 1 of 2)
4-225
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
Table 4-VIII. Scaler Outputs (Stages 1-17)
Output
Frequency
Period
Pulse Polarity
FS09, FS09
-
F09A, F09B, F09D
200 pps
5.0 msec.
Positive
F09A, F09B
Negative
FS10
-
F10A, F10B
100 pps
10 msec.
Positive
F10A, F10B
Negative
FS11
50 pps
20. 0 msec.
-
F11A, FI IB
Positive
FS12
25 pps
40. 0 msec.
-
F12A, F12B
Positive
FS13
12. 5 pps
80. 0 msec.
-
F13A, F13B
Positive
FS14
6. 25 pps
160 msec.
-
F14A, F14B
Positive
FS15
3. 125 pps
320 msec.
-
F 1 5 A , F15B
Positive
FS16
1. 5625 pps
640 msec.
-
F16A, F16B
Positive
FS17
-
F17A, F17B
0.78125 pps
1.3 sec.
Positive
F17A, F17B
Negative
NOTE: All pulse outputs (F01A, FOIB etc.) are
10 fj sec, wide regardless of frequency.
(Sheet 2 of 2)
4-226
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
OODSET
•^^3430^0-
34308^0 QJ
i
5^3432^0—0-:
» 34 ' j 34324^0-
337
H
Figure 4-122. Time Pulse
Generator Logic
4-227/4-228
ND-1021042
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM MANUAL
- * - - -
The waveforms for the time pulse generator are shown in figure 4-123. Inputs
ODDSET and EVNSET each occur at a 512 kpps rate, but are 90 degrees out of phase
with each other^jP Consequently, even though the driving inputs are 0.75 microsecond
wide, the effective drive rate of both inputs combined is twice the rate of the input.
The period between each ODDSET and EVNSET pulse is 0.97 microsecond. However,
time pulse outputs T01 through T12 are 0.75 microsecond wide.
Signal GOJAM forces the time pulse generator to indicate T12 time by resetting
the T1 through Til flip-flops, and setting the T12 flip-flop. Forcing the time pulse
generator in this manner enables the cycling to be restarted beginning with T01, after
a condition occurs which initiated GOJAM.
Additional drive for several of the timing pulse outputs is provided by gates lo¬
cated on modules A2, A3, A12, and A24. These gates are illustrated in figure 4-122.
The outputs (for example, T01 from gate 49421 on A24, T02 from gate 37359 on A2,
etc.) are in parallel with the outputs developed by the flip-flops on module A2.
4-5.3. 6 Sync and Timing Logic. The sync and timing logic, figure 4-124, generates
synchronization, timing, and gating pulses for use within the LGC subsystems, and
synchronization pulses for systems external to the LGC. These signals are developed
as a function of the ring counter, strobe pulse generator, and scaler outputs.
The synchronization outputs to the external systems as well as the LGC oscillator,
clock divider logic, and the scaler outputs are generated both during normal operation
and during standby. The gates on modules Al, A2, and A24 are controlled so that the
supply voltage is uninterrupted when the LGC is switched to standby operation.
4-5.4 SF.QTTRMTF. GENERATOR. The sequence generator contains the order code pro¬
cessor, coifijSid generator, and control pulse generator. The sequence generator
executes th J^fc*uctions stored in memory by producing control pulses which regulate
the data fUftflpthe computer. The manner in which the data flow is regulated among
the various functional areas of the computer and between the elements of the central
processor ca#es the data to be processed according to the specifications of each machine
instruction! if
The oij
control, am
processor
generator di
commands
control pu
instruction,
the executio
ode processor receives signals from the central processor, priority
heral equipment. The order code signals are stored in the order code
yerted to coded signals for the command generator. The command
signals and produces instruction commands. The instruction
;t to the control pulse generator to produce a particular sequence of
on the instruction being executed. At the completion of each
ddf%|k>de signals are sent to the order code processor to continue
program.
r
*
ND 1021042
MANUAL
ODDSET
EVNSET
T09
TIO
Til
T 12 SET
fl2
To?
#
T02
*_>
T05
T06
V
TOT
T08
UM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
- £ -
Figure 4-123. Time Pulse Generator Wavefc?
FS06
311
caTq 1
*310
315 .
r UDb f
316 lnvlN>
- j 49342yO - <
F05B 4
310
*314
FS06 1
FS07A <
307
*310
*314
poT
F05B <
FS06 4
FSOB 4
FS09 4
304
A 24
313 \ ^\_ 1
• ) 46314^0 — - j 46313^0 O
T2P J
TO
PRIORITY
CONTROL
|
WOVR V - =
0^F^_
J4€26l |
1 AI9
SYNC 14 J
TO LGC
POWER
SUPPLY
AS3
'* * ■
LEM PRIMARY GUIDANCE, NAVIGATION, AND CONTROL SYSTEM
ND-1021042
MANUAL
r
i
-i
FSI7
FSI6
FS07A
A24
_1
OUTBITS
I
n.
r ?
/ '
. i
F04B
Figure 4-124. Sync and Timing Logic
4-231/4-232
/
' *>
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